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PDF AD5725 Data sheet ( Hoja de datos )
| Número de pieza | AD5725 | |
| Descripción | Voltage Output DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Quad, 12-Bit, Parallel Input,
Unipolar/Bipolar, Voltage Output DAC
AD5725
FEATURES
+5 V to ±15 V operation
Unipolar or bipolar operation
±0.5 LSB max INL error, ±1 LSB max DNL error
Settling time: 10 µs max (10 V step)
Double-buffered inputs
Simultaneous updating via LDAC
Asynchronous CLR to zero/mid scale
Readback
Operating temperature range: −40°C to +85°C
iCMOS® process technology
APPLICATIONS
Industrial automation
Closed-loop servo control, process control
Automotive test and measurement
Programmable logic controllers
GENERAL DESCRIPTION
The AD5725 is a quad, 12-bit, parallel input, voltage output
digital-to-analog converter that offers guaranteed monotonicity,
integral nonlinearity (INL) of ±0.5 LSB maximum and 10 µs
maximum settling time.
Output voltage swing is set by two reference inputs, VREFP and
VREFN. By setting the VREFN input to 0 V and the VREFP to a
positive voltage, the DAC provides a unipolar positive output
range. A similar configuration with VREFP at 0 V and VREFN at a
negative voltage provides a unipolar negative output range.
Bipolar outputs are configured by connecting both VREFP and
VREFN to nonzero voltages. This method of setting output voltage
ranges has advantages over the bipolar offsetting methods
because it is not dependent on internal and external resistors
with different temperature coefficients.
VL
A0
A1
R/W
CS
DB0
TO
DB11
FUNCTIONAL BLOCK DIAGRAM
AVSS AVDD
VREFP
I/O
REGISTER
AND
CONTROL
LOGIC
12
12
AD5725
INPUT
REG A
INPUT
REG B
INPUT
REG C
INPUT
REG D
DAC 12
REG A
DAC A
DAC 12
REG B
DAC B
DAC 12
REG C
DAC C
DAC 12
REG D
DAC D
DGND
CLR
LDAC
Figure 1.
VREFN
VOUTA
VOUTB
VOUTC
VOUTD
Digital controls allow the user to load or read back data from
any DAC, load any DAC, and transfer data to all DACs at
one time.
The AD5725 is available in a 28-lead SSOP package. It can be
operated from a wide variety of supply and reference voltages,
with supplies ranging from single +5 V to ±15 V, and references
from +2.5 V to ±10 V. Power dissipation is less than 270 mW
with ±15 V supplies and only 40 mW with a +5 V supply.
Operation is specified over the temperature range of −40°C
to +85°C.
iCMOS® Process Technology
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, and increased ac and dc performance.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD5725
AC PERFORMANCE CHARACTERISTICS1
AVDD = +15 V/+5 V, AVSS = −15 V/−5 V/0 V, DGND = 0 V; VREFP = +10 V/+2.5 V; VREFN = −10 V/−2.5 V/0 V, VL = 5 V. All specifications
TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
Slew Rate
Analog Crosstalk
Digital Feedthrough
A Grade B Grade Unit
10 10 µs typ
7 7 µs typ
2.2 2.2 V/µs typ
72 72 dB typ
5 5 nV-s typ
Test Conditions/Comments
To 0.01%, 10 V step, RL = 1 kΩ
To 0.01%, 2.5 V step, RL = 1 kΩ
10% to 90%
1 Guaranteed by design and characterization, not production tested.
Rev. C | Page 5 of 20
5 Page 
Data Sheet
0.3
0.2 DAC A
DAC B
DAC C
DAC D
0.1
0
–0.1
AVDD = +15V
–0.2
AVSS = –15V
VREFP = +10V
VREFN = –10V
TA = 25°C
–0.3
0 500 1000
1500
2000
2500
3000
3500
4000
DAC (Code)
Figure 13. Channel-to-Channel Matching (VSUPPLY = ±15 V)
0.3
0.2 DAC A
DAC B
DAC C
0.1 DAC D
0
–0.1
–0.2
AVDD = 5V
AVSS = 0V
–0.3 VREFP = 2.5V
VREFN = 0V
TA = 25°C
–0.4
0 500 1000
1500
2000
2500
3000
3500
4000
DAC (Code)
Figure 14. Channel-to-Channel Matching (VSUPPLY = +5 V)
16
14
12
10
8
6
4 AVDD = +15V
AVSS = –15V
2
VREFN = –10V
DIGITAL INPUTS HIGH
TA = 25°C
0
–7 –5 –3 –1 1 3 5 7
VREFP (V)
Figure 15. IDD vs. VREFP
9 11 13
AD5725
0.4
0.3
+85°C
0.2
+25°C
–40°C
0.1
0
–0.1
–0.2
AVDD = +15V
–0.3
AVSS = –15V
VREFP = +10V
VREFN = –10V
–0.4
0 500 1000
1500
2000
2500
3000
DAC (Code)
Figure 16. INL vs. DAC Code
3500
4000
0.20
0.15
0.10
+85°C
+25°C
–40°C
0.05
0
–0.05
–0.10
AVDD = +15V
–0.15
AVSS = –15V
VREFP = +10V
VREFN = –10V
–0.20
0 500 1000
1500
2000
2500
3000
DAC (Code)
Figure 17. DNL vs. DAC Code
3500
4000
1.7995
AVDD = +15V
1.5995 AVSS = –15V
VREFP = +10V
VREFN = –10V
TA = 25°C
1.3995
1.1995
0.9995
0.7995
0.5995
0.3995
0.1995
–0.0005
0
500 1000 1500 2000 2500 3000 3500 4000
DAC (Code)
Figure 18. IVREFP vs. DAC Code
Rev. C | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD5725.PDF ] | |
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