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PDF VIPer0P Data sheet ( Hoja de datos )
| Número de pieza | VIPer0P | |
| Descripción | Zero-power off-line high voltage converter | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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VIPer0P
Zero-power off-line high voltage converter
Datasheet - production data
Figure 1: Basic application schematic
Features
Smart stand-by architecture using the Zero
Power Mode (ZPM)
ZPM management by MCU easily realizable
800 V avalanche-rugged power MOSFET
allowing ultra wide VAC input range to be
covered
Embedded HV startup and sense-FET
Current mode PWM controller
Drain current limit protection (OCP)
Wide supply voltage range: 4.5 V to 30 V
Self-supply option allows to remove the
auxiliary winding or bias components
Minimized system input power consumption:
Less than 4 mW @ 230 VAC in ZPM
Less than 10 mW @ 230 VAC in no-load
condition
Less than 400 mW @ 230 VAC with 250
mW load
Jittered switching frequency reduces the
EMI filter cost
60 kHz ±7% (type L)
120 kHz ±7% (type H)
Embedded E/A with 1.2 V reference and
separate ground for easy negative voltage
setting
Protections with automatic restart:
overload/short circuit (OLP), max. duty cycle
counter, VCC clamp
Pulse-skip protection to prevent flux-
runaway
Embedded thermal shutdown
Built in soft start for improved system
reliability
Applications
SMPS for home appliances, home
automation, industrial, lighting and
consumers
Description
The device is a high-voltage converter that
smartly integrates an 800 V avalanche rugged
power MOSFET with PWM current-mode control.
The power MOSFET with 800 V breakdown
voltage allows extended input voltage range to be
applied, as well as to reduce the size of the
DRAIN snubber circuit. This IC is capable of
meeting the most stringent energy-saving
standards as it has very low consumption and
operates in pulse frequency modulation under
light load. The Zero-Power mode (ZPM) feature
enables the IC to work in an idle state, where the
system is totally shutdown. An MCU can be
easily connected to the IC for smart ZPM
management and it can be supplied by the IC
itself during the idle state. The design of flyback,
buck and buck boost converters is supported.
The integrated HV startup, sense FET, error
amplifier and oscillator with jitter allow a complete
application to be designed with a minimum
component count. In flyback non isolated
topology, a negative output voltage is easily set
thanks to the integrated error amplifier with
separate ground.
September 2015
DocID028423 Rev 1
This is information on a product in full production.
1/36
www.st.com
1 page  
VIPer0P
1 Pin setting
Figure 2: Connection diagram
Pin setting
PGND
EAGND
VCC
SGND
FB
COMP
ON
OFF
VIPer0P
DRAIN
DRAIN
DRAIN
DRAIN
N.C.
N.C.
N.C.
N.C.
GIPD210420151108MT
The PCB copper area for heat dissipation has to be provided under the DRAIN
pins.
SO16N
1
2
3
4
5
6
Name
PGND
EAGND
VCC
SGND
FB
COMP
Table 1: Pin description
Function
Power ground and MOSFET source. The pulsed current flowing through
the Power MOSFET must be closed on this pin. The pin must be connected
to the same ground plan of SGND with the shortest track.
Error amplifier ground reference. In case of non-isolated flyback converter
with negative output voltage, this pin can be connected directly to the
negative rail. Otherwise, in case of positive output voltage, the pin must be
shorted to SGND.
Controller supply. An external storage capacitor has to be connected
across this pin and SGND. The pin, internally connected to the high-voltage
current source, provides the VCC capacitor charging current at startup and, if
self-supply mode is selected, also during steady-state operation. A small
bypass capacitor (0.1 μF typ.) in parallel, placed as close as possible to the
IC, is also recommended, for noise filtering purpose.
Signal ground. All of the groundings of bias components must be tied to a
trace going to this pin and kept separate from the pulsed current return.
Direct feedback. It is the inverting input of the internal transconductance
E/A, which is internally referenced to 1.2 V with respect to EAGND. In case
of non-isolated converter, the output voltage information is directly fed into
the pin through a voltage divider. In case of primary regulation, the FB
voltage divider is connected to the VCC. The E/A is disabled soldering FB to
EAGND.
Compensation. It is the output of the internal E/A. A compensation network
is placed between this pin and SGND to achieve stability and good dynamic
performance of the control loop. In case of secondary feedback, the internal
E/A must be disabled and the COMP directly driven by the optocoupler to
control the DRAIN peak current setpoint.
DocID028423 Rev 1
5/36
5 Page 
VIPer0P
Typical electrical characteristics
3 Typical electrical characteristics
Figure 3: IDLIM vs TJ
IDLIM/(IDLIM@25°C)
1.1
ION (µA)
30
Figure 4: ION vs VON
25
20
1 15
10
5
0.9
-50
0
0 50 100 150 2.75
Tj(°C)
GIPD160720151000MT
3.25 3.75 4.25
VON (V)
GIPD160720151001MT
Figure 5: FOSC vs TJ
FOSC /(FOSC @25°C)
1.05
Figure 6: VHV_START vs TJ
VHV_START/(VHV_START@25°C)
1.5
1.25
11
0.75
0.95
-50
0.5
0 50 100 150 -50
Tj(°C)
GIPD160720151002MT
0 50 100 150
Tj(°C)
GIPD160720151004MT
DocID028423 Rev 1
11/36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet VIPer0P.PDF ] | |
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