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HEF4027B-Q100 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer HEF4027B-Q100
Beschreibung Dual JK flip-flop
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 13 Seiten
HEF4027B-Q100 Datasheet, Funktion
HEF4027B-Q100
Dual JK flip-flop
Rev. 1 — 26 June 2013
Product data sheet
1. General description
The HEF4027B-Q100 is an edge-triggered dual JK flip-flop which features independent
set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted
when CP is LOW, and transferred to the output on the positive-going edge of the clock.
The active HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are
independent and override the J, K, and CP inputs. The outputs are buffered for best
system performance. Schmitt trigger action makes the clock input highly tolerant of slower
rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 3)
Specified from 40 C to +85 C
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-833, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Complies with JEDEC standard JESD 13-B
3. Applications
Registers
Counters
Control circuits






HEF4027B-Q100 Datasheet, Funktion
NXP Semiconductors
HEF4027B-Q100
Dual JK flip-flop
11. Dynamic characteristics
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 C; for test circuit, see Figure 7; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Extrapolation formula[1] Min Typ Max Unit
tPHL HIGH to LOW
CP Q, Q;
5V
propagation delay see Figure 4
10 V
78 ns + (0.55 ns/pF)CL
29 ns + (0.23 ns/pF)CL
-
-
105 210 ns
40 80 ns
15 V
22 ns + (0.16 ns/pF)CL
-
30 60 ns
CD Q;
see Figure 4
5V
10 V
93 ns + (0.55 ns/pF)CL
33 ns + (0.23 ns/pF)CL
-
-
120 240 ns
45 90 ns
15 V
27 ns + (0.16 ns/pF)CL
-
35 70 ns
SD Q;
see Figure 4
5V
10 V
113 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
-
-
140 280 ns
55 110 ns
15 V
32 ns + (0.16 ns/pF)CL
-
40 80 ns
tPLH LOW to HIGH
CP Q, Q;
5V
propagation delay see Figure 4
10 V
58 ns + (0.55 ns/pF)CL
27 ns + (0.23 ns/pF)CL
-
-
85 170 ns
35 70 ns
15 V
22 ns + (0.16 ns/pF)CL
-
30 60 ns
CD Q;
see Figure 4
5V
10 V
48 ns + (0.55 ns/pF)CL
24 ns + (0.23 ns/pF)CL
-
-
75 150 ns
35 70 ns
15 V
17 ns + (0.16 ns/pF)CL
-
25 50 ns
SD Q;
see Figure 4
5V
10 V
43 ns + (0.55 ns/pF)CL
19 ns + (0.23 ns/pF)CL
-
-
70 140 ns
30 60 ns
15 V
17 ns + (0.16 ns/pF)CL
-
25 50 ns
tt
transition time
see Figure 4
5 V [2]
10 ns + (1.00 ns/pF)CL
-
60 120 ns
10 V
9 ns + (0.42 ns/pF)CL
-
30 60 ns
15 V
6 ns + (0.28 ns/pF)CL
-
20 40 ns
tsu set-up time
J, K CP;
see Figure 5
5V
10 V
50 25 -
30 10 -
ns
ns
15 V
20 5
-
ns
th hold time
J, K CP;
see Figure 5
5V
10 V
25 0
20 0
-
-
ns
ns
15 V
15 5
-
ns
tW pulse width
CP LOW;
minimum width,
see Figure 5
5V
10 V
15 V
80 40 -
30 15 -
24 12 -
ns
ns
ns
SD, CD HIGH;
minimum width,
see Figure 6
5V
10 V
15 V
90 45 -
40 20 -
30 15 -
ns
ns
ns
trec recovery time
SD, CD inputs; 5 V
see Figure 6
10 V
+20 15 -
+15 10 -
ns
ns
15 V
+10 5 -
ns
HEF4027B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 June 2013
© NXP B.V. 2013. All rights reserved.
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HEF4027B-Q100 pdf, datenblatt
NXP Semiconductors
HEF4027B-Q100
Dual JK flip-flop
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
HEF4027B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 June 2013
© NXP B.V. 2013. All rights reserved.
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