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PDF TLV320AIC3104 Data sheet ( Hoja de datos )
| Número de pieza | TLV320AIC3104 | |
| Descripción | LOW-POWER STEREO AUDIO CODEC | |
| Fabricantes | Burr-Brown | |
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1. TLV320AIC3104  Hay una vista previa y un enlace de descarga de TLV320AIC3104 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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BurrĆBrown Products
from Texas Instruments
TLV320AIC3104
SLAS510A – FEBRUARY 2007 – REVISED JULY 2007
LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
FEATURES
• Stereo Audio DAC
– 102-dBA Signal-to-Noise Ratio
– 16/20/24/32-Bit Data
– Supports Sample Rates From 8 kHz to 96
kHz
– 3D/Bass/Treble/EQ/De-Emphasis Effects
– Flexible Power Saving Modes and
Performance are Available
• Stereo Audio ADC
– 92-dBA Signal-to-Noise Ratio
– Supports Sample Rates From 8 kHz to 96
kHz
– Digital Signal Processing and Noise
Filtering Available During Record
• Six Audio Input Pins
– One Stereo Pair of Single-Ended Inputs
– One Stereo Pair of Fully Differential Inputs
• Six Audio Output Drivers
– Stereo Fully Differential or Single-Ended
Headphone Drivers
– Fully Differential Stereo Line Outputs
• Low Power: 14-mW Stereo 48-kHz Playback
With 3.3-V Analog Supply
• Ultralow-Power Mode with Passive Analog
Bypass
• Programmable Input/Output Analog Gains
• Automatic Gain Control (AGC) for Record
• Programmable Microphone Bias Level
• Programmable PLL for Flexible Clock
Generation
• I2C Control Bus
• Audio Serial Data Bus Supports I2S,
Left/Right-Justified, DSP, and TDM Modes
• Extensive Modular Power Control
• Power Supplies:
– Analog: 2.7 V–3.6 V.
– Digital Core: 1.525 V–1.95 V
– Digital I/O: 1.1 V–3.6 V
• Package: 5-mm × 5-mm 32-Pin QFN
APPLICATIONS
• Digital Cameras
• Smart Cellular Phones
• PDAs
• Portable Computing
• Communication
• Entertainment Applications
DESCRIPTION
The TLV320AIC3104 is a low-power stereo audio
codec with stereo headphone amplifier, as well as
multiple inputs and outputs that are programmable in
single-ended or fully differential configurations.
Extensive register-based power control is included,
enabling stereo 48-kHz DAC playback as low as 14
mW from a 3.3-V analog supply, making it ideal for
portable battery-powered audio and telephony
applications.
The record path of the TLV320AIC3104 contains
integrated microphone bias, digitally controlled stereo
microphone preamplifier, and automatic gain control
(AGC), with mix/mux capability among the multiple
analog inputs. Programmable filters are available
during record which can remove audible noise that
can occur during optical zooming in digital cameras.
The playback path includes mix/mux capability from
the stereo DAC and selected inputs, through
programmable volume controls, to the various
outputs.
The TLV320AIC3104 contains four high-power
output drivers as well as two fully differential output
drivers. The high-power output drivers are capable of
driving a variety of load configurations, including up
to four channels of single-ended 16-Ω headphones
using ac-coupling capacitors, or stereo 16-Ω
headphones in a capless output configuration.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
1 page  
www.ti.com
TERMINAL
NAME
QFN NO.
AVDD
25
AVSS1
17
AVSS2
26
BCLK
2
DIN 4
DOUT
5
DRVDD
18
DRVDD
24
DRVSS
21
DVDD
32
DVSS
6
HPLCOM
20
HPLOUT
19
HPRCOM
22
HPROUT
23
IOVDD
7
LEFT_LOM
28
LEFT_LOP
27
MCLK
1
MIC1LM/LINE1LM
11
MIC1LP/LINE1LP
10
MIC1RM/LINE1RM
13
MIC1RP/LINE1RP
12
MIC2L/LINE2L/MICDET
14
MIC2R/LINE2R
16
MICBIAS
15
RESET
31
RIGHT_LOM
30
RIGHT_LOP
29
SCL 8
SDA
9
WCLK
3
TLV320AIC3104
SLAS510A – FEBRUARY 2007 – REVISED JULY 2007
Table 1. TERMINAL FUNCTIONS
DESCRIPTION
I/O
— Analog DAC voltage supply, 2.7 V–3.6 V
— Analog ADC ground supply, 0 V
— Analog DAC ground supply, 0 V
I/O Audio serial data bus bit clock input/output
I Audio serial data bus data input
O Audio serial data bus data output
— Analog ADC and output driver voltage supply, 2.7 V–3.6 V
— Analog output driver voltage supply, 2.7 V–3.6 V
— Analog output driver ground supply, 0 V
— Digital core voltage supply, 1.525 V–1.95 V
— Digital core / I/O ground supply, 0 V
O High-power output driver (left – or multifunctional)
O High-power output driver (left +)
O High-power output driver (right – or multifunctional)
O High-power output driver (right +)
— Digital I/O voltage supply, 1.1 V–3.6 V
O Left line output (–)
O Left line output (+)
I Master clock input
I Left input – (diff only)
I Left input 1 (SE) or left input + (diff)
I Right input – (diff only)
I Right input 1 (SE) or right input + (diff)
I Left input 2 (SE); can support microphone detection
I Right input 2 (SE)
O Microphone bias voltage output
I Reset
O Right line output (–)
O Right line output (+)
I/O I2C serial clock input
I/O I2C serial data input/output
I/O Audio serial data bus word clock input/output
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5
5 Page 
www.ti.com
AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS
All specifications at +25°C, DVDD = 1.8 V.
WCLK
TLV320AIC3104
SLAS510A – FEBRUARY 2007 – REVISED JULY 2007
td(WS)
BCLK
td(DO-WS)
td(DO-BCLK)
SDOUT
tS(DI)
th(DI)
SDIN
PARAMETER
IOVDD = 1.1 V
MIN MAX
td(WS)
td(DO-WS)
td(DO-BCLK)
ts(DI)
th(DI)
tr
tf
ADWS/WCLK delay time
ADWS/WCLK to DOUT delay time
BCLK to DOUT delay time
DIN setup time
DIN hold time
Rise time
Fall time
50
50
50
10
10
30
30
NOTE: All timing specifications are measured at characterization but not tested at final test.
Figure 1. I2S/LJF/RJF Timing in Master Mode
IOVDD = 3.3 V
MIN MAX
15
20
15
6
6
10
10
T0145-01
UNIT
ns
ns
ns
ns
ns
ns
ns
Submit Documentation Feedback
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TLV320AIC3104.PDF ] | |
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