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TM023KDH18 Schematic ( PDF Datasheet ) - TIANMA

Teilenummer TM023KDH18
Beschreibung Display Module
Hersteller TIANMA
Logo TIANMA Logo 




Gesamt 28 Seiten
TM023KDH18 Datasheet, Funktion
SHANGHAI TIANMA MICRO-ELECTRONICS
Coversheet
TM023KDH18 V1.0
MODEL NO. :
ISSUED DATE:
VERSION :
TM023KDH18
2010-05-21
Ver 1.0
Preliminary Specification
Final Product Specification
Customer :
Approved by
Notes
SHANGHAI TIANMA Confirmed :
Prepared by
Checked by
Approved by
This technical specification is subjected to change without notice
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 1 of 28






TM023KDH18 Datasheet, Funktion
SHANGHAI TIANMA MICRO-ELECTRONICS
No Symbol
I/O
Description
32 GND
P Power Ground
33 NC
-- No connection
34 NC
-- No connection
35 NC
-- No connection
36 NC
-- No connection
TM023KDH18 V1.0
Remark
Table 2.1 input terminal pin assignment
Note: I/O definition
I-----Input
O---Output
P----Power/ Ground NC--- No Connection
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 6 of 28

6 Page









TM023KDH18 pdf, datenblatt
SHANGHAI TIANMA MICRO-ELECTRONICS
TM023KDH18 V1.0
5.2 Interface Timing Parameters
Normal Write Mode
Signal Symbol
Parameter
Spec
Min Max Unit
Description
RS
tAST
tAHT
Address setup time
0
Address hold time(Write/Read) 10
-
ns
tCHW Chip select “H” pulse width
0
tCS Chip select setup time (Write) 15
tRCS Chip select setup time (Read 45
CS
tRCSFM
ID)
Chip select setup time (Read
355
-
ns
FM)
-
-
tCSF Chip select wait
time(Write/Read)
10
WR
RDID
RDFM
tWC
tWRH
tWRL
tRC
tRDH
tRDL
tRCFM
tRDHFM
Write cycle
Control pulse “H” duration
Control pulse “L” duration
Read cycle (ID)
Control pulse “H” duration (ID)
Control pulse “L” duration (ID)
Read cycle (FM)
Control pulse “H” duration
(FM)
65
15
15
160
90
45
450
90
-
-
-
ns -
ns When read ID data
ns
When read from
frame memory
DB[15:0],
tRDLFM
tDST
tDHT
tRAT
tRATFM
tODH
Control pulse “L” duration (FM)
Data setup time
Data hold time
Read access time (ID)
Read access time (FM)
Output disable time
355
10
10
-
-
20
-
-
40
340
80
For maximum
ns
CL=30pF
For minimum
CL=8pF
Table 5.2 CPU Interface Timing Parameters
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 12 of 28

12 Page





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