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Teilenummer | 74HC373 |
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Beschreibung | Octal D-type transparent latch | |
Hersteller | NXP Semiconductors | |
Logo | ||
Gesamt 25 Seiten 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Rev. 6 — 26 February 2016
Product data sheet
1. General description
The 74HC373; 74HCT373 is an octal D-type transparent latch with 3-state outputs. The
device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data
at the inputs enter the latches. In this condition the latches are transparent, a latch output
will change each time its corresponding D-input changes. When LE is LOW the latches
store the information that was present at the inputs a set-up time preceding the
HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches. Inputs include clamp diodes. This enables the use of current limiting resistors to
interface inputs to voltages in excess of VCC.
2. Features and benefits
Input levels:
For 74HC373: CMOS level
For 74HCT373: TTL level
3-state non-inverting outputs for bus oriented applications
Common 3-state output enable input
Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573
Complies with JEDEC standard no. 7 A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74HC373D 40 C to +125 C SO20
74HCT373D
74HC373DB 40 C to +125 C SSOP20
74HCT373DB
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
Version
SOT163-1
SOT339-1
NXP Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
VCC
VI
VO
Tamb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
9. Static characteristics
74HC373
Min Typ Max
2.0 5.0 6.0
0 - VCC
0 - VCC
40 +25 +125
- - 625
- 1.67 139
- - 83
74HCT373
Min Typ Max
4.5 5.0 5.5
0 - VCC
0 - VCC
40 +25 +125
---
- 1.67 139
---
Unit
V
V
V
C
ns/V
ns/V
ns/V
Table 6. Static characteristics 74HC373
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 25 C
VIH HIGH-level input voltage
VIL LOW-level input voltage
VOH HIGH-level output voltage
VOL LOW-level output voltage
II input leakage current
IOZ OFF-state output current
ICC supply current
CI input capacitance
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
VCC = 6.0 V; IO = 0 A;
VI = VCC or GND
Min
1.5
3.15
4.2
-
-
-
-
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
-
-
-
-
Typ
1.2
2.4
3.2
0.8
2.1
2.8
-
2.0
4.5
6.0
4.32
5.81
0
0
0
0.15
0.16
-
-
-
3.5
Max Unit
-V
-V
-V
0.5 V
1.35 V
1.8 V
-
-V
-V
-V
-V
-V
0.1 V
0.1 V
0.1 V
0.26 V
0.26 V
0.1 A
0.5 A
8.0 A
- pF
74HC_HCT373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 26 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 25
6 Page NXP Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Table 8. Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min Typ Max Unit
Tamb = 40 C to +125 C
tpd propagation delay
Dn to Qn; see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
LE to Qn; see Figure 9
[1]
-
-
-
- 225 ns
- 45 ns
- 38 ns
ten enable time
tdis disable time
tt transition time
tW pulse width
tsu set-up time
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
OE to Qn; see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
OE to Qn; see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Qn; see Figure 8 and Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
LE HIGH; see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Dn to LE; see Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
[2]
-
-
-
[3]
-
-
-
[4]
-
-
-
- 265 ns
- 53 ns
- 45 ns
- 225 ns
- 45 ns
- 38 ns
- 225 ns
- 45 ns
- 38 ns
- 90 ns
- 18 ns
- 15 ns
120 -
24 -
20 -
- ns
- ns
- ns
75 -
15 -
13 -
- ns
- ns
- ns
74HC_HCT373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 26 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
12 of 25
12 Page | ||
Seiten | Gesamt 25 Seiten | |
PDF Download | [ 74HC373 Schematic.PDF ] |
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