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71M6513H Schematic ( PDF Datasheet ) - Teridian

Teilenummer 71M6513H
Beschreibung 3-Phase Energy Meter IC
Hersteller Teridian
Logo Teridian Logo 




Gesamt 30 Seiten
71M6513H Datasheet, Funktion
19-5360; Rev 3; 9/11
71M6513/71M6513H
A Maxim Integrated Products Brand
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
GENERAL DESCRIPTION
The 71M6513 is a highly integrated system-on-chip SoC with an MPU core,
real-time clock (RTC), flash, and LCD driver. Our Single Converter
Technology® with a 21-bit delta-sigma ADC, six analog inputs, digital tem-
perature compensation, precision voltage reference, and 32-bit computation
engine (CE) supports a wide range of poly-phase metering applications with
very few low-cost external components. A 32kHz crystal time base for the
entire system and internal battery-backup support for RAM and RTC further
reduce system cost.
Maximum design flexibility is supported with multiple UARTs, I2C, a power-
fail comparator, a 5V LCD charge pump, up to 22 DIO pins, and an in-
system programmable flash. The device is offered in high (0.1%) and
standard (0.5%) accuracy versions for multifunction residential/commercial
meter applications requiring multiple voltage/current inputs and complex
LCD or DIO configurations.
A complete array of ICE and development tools, programming libraries and
reference designs enable rapid development and certification of meters that
meet most demanding worldwide electricity metering standards.
LIVE CT /COIL
NEUTRAL
LIVE
LOAD
LIVE
POWER SUPPLY
AMR
CONVERTER
IA
VA
IB
VB
IC
VC
VOLTAGE REF
VREF
VBIAS
SERIAL PORTS
TX
RX
V3.3A V3.3D GNDA GNDD
5V BOOST
TERIDIAN
VDRV
71M6513 REGULATOR
VBAT
V2.5
TEMP SENSOR
RAM
COMPUTE
ENGINE
LCD DRIVER
DIO, PULSE
VLCD
COM0..3
SEG0..23
SEG 24..27
DIO 0..11
BATTERY
3/5V LCD
88.88.8888
FEATURES
Wh Accuracy < 0.1% Over 2,000:1
Current Range
Exceeds IEC 62053/ANSIC 12.20
Voltage Reference
< 10ppm/°C (71M6513H)
< 40ppm/°C (71M6513)
Six Sensor Inputs—VDD Referenced
Auxiliary Analog Input for Neutral
Current
Low Jitter Wh/VARh Pulse Outputs
Pulse Count For Pulse Outputs
Four-Quadrant Metering
Phase Sequencing
Line Frequency Count for RTC
Digital Temperature Compensation
Sag Detection
Independent 32-Bit Compute Engine
40-70Hz Line Frequency Range with
Same Calibration
Phase Compensation (±7°)
Battery Backup for RAM and RTC
22mW at 3.3V, 7.2µW Backup
Flash Memory Option with Security
8-Bit MPU (80515)—One Clock
Cycle per Instruction
LCD Driver (168 Pixels)
High-Speed SSI Serial Output
RTC for Time-of-Use Functions
Hardware Watchdog Timer
Up to 22 General-Purpose I/O Pins
64KB Flash, 7KB RAM
Two UARTs for IR and AMR
100-Pin LQFP Package
IR
POWER
FAULT
Etc.
SENSE
DRIVE
RX
TX
COMPARATOR
V1
V2
V3
FLASH
MPU
RTC
TIMERS
ICE
SEG 32..41
DIO 12..21
OSC/PLL
XIN
XOUT
MISC
EEPROM
32 kHz
Single Converter Technology is a registered trademark of
Maxim Integrated Products, Inc.
© 2005-2011 Teridian Semiconductor Corporation
Page: 1 of 104






71M6513H Datasheet, Funktion
71M6513/71M6513H
A Maxim Integrated Products Brand
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Figure 34: Error Band for VREF over Temperature (High-Accuracy Parts) ..................................................................... 83
Figure 33: Connecting LCDs ...................................................................................................................................... 84
Figure 34: LCD Boost Circuit...................................................................................................................................... 85
Figure 35: EEPROM Connection................................................................................................................................. 85
Figure 36: Interfacing RX to a 0-5V Signal .................................................................................................................. 86
Figure 37: Connection for Optical Components ........................................................................................................... 87
Figure 38: Voltage Divider for V1 ............................................................................................................................... 87
Figure 39: External Components for RESETZ .............................................................................................................. 88
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles.......................................................... 9
Table 2: CE DRAM Locations for ADC Results......................................................................................... 12
Table 3: Standard Meter Equations (inputs shown gray are scanned but not used for calculation).............. 13
Table 4: Stretch Memory Cycle Width ...................................................................................................... 17
Table 5: Internal Data Memory Map ......................................................................................................... 18
Table 6: Special Function Registers Locations ......................................................................................... 18
Table 7: Special Function Registers Reset Values.................................................................................... 20
Table 8: PSW Register Flags................................................................................................................... 20
Table 9: PSW bit functions ...................................................................................................................... 21
Table 10: Port Registers.......................................................................................................................... 22
Table 11: Special Function Registers....................................................................................................... 23
Table 12: Baud Rate Generation.............................................................................................................. 24
Table 13: UART Modes ........................................................................................................................... 24
Table 14: The S0CON Register................................................................................................................. 24
Table 15: The S1CON register .................................................................................................................. 25
Table 16: The S0CON Bit Functions.......................................................................................................... 25
Table 17: The S1CON Bit Functions.......................................................................................................... 26
Table 18: The TMOD Register ................................................................................................................. 26
Table 19: TMOD Register Bit Description................................................................................................. 27
Table 20: Timers/Counters Mode Description........................................................................................... 27
Table 21: The TCON Register .................................................................................................................. 27
Table 22: The TCON Register Bit Functions ............................................................................................. 28
Table 23: Timer Modes............................................................................................................................ 28
Table 24: The PCON Register ................................................................................................................. 28
Table 25: The IEN0 Register (see also Table 32)...................................................................................... 29
Table 26: The IEN0 Bit Functions (see also Table 32)............................................................................... 29
Table 27: The IEN1 Register (see also Tables 30/31)............................................................................... 29
Table 28: The IEN1 Bit Functions (see also Tables 30/31)........................................................................ 29
Table 29: The IP0 Register (see also Table 45)........................................................................................ 30
Table 30: The IP0 bit Functions (see also Table 45) ................................................................................. 30
Table 31: The WDTREL Register............................................................................................................. 30
Table 32: The WDTREL Bit Functions...................................................................................................... 30
Table 33: The IEN0 Register.................................................................................................................... 32
Table 34: The IEN0 Bit Functions............................................................................................................. 32
Table 35: The IEN1 Register ................................................................................................................... 32
Table 36: The IEN1 Bit Functions ............................................................................................................ 32
Table 37: The IEN2 Register ................................................................................................................... 33
Table 38: The IEN2 Bit Functions ............................................................................................................ 33
Page: 6 of 104
© 2005-2011 Teridian Semiconductor Corporation

6 Page









71M6513H pdf, datenblatt
71M6513/71M6513H
A Maxim Integrated Products Brand
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Computation Engine (CE)
The CE, a dedicated 32-bit RISC processor, performs the precision computations necessary to accurately measure energy.
The CE calculations and processes include:
Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when
multiplied with the constant sample time).
Frequency-insensitive delay cancellation on all six channels (to compensate for the delay between samples caused
by the multiplexing scheme).
90° phase shifter (for VAR calculations).
Pulse generation.
Monitoring of the input signal frequency (for frequency and phase information).
Monitoring of the input signal amplitude (for sag detection).
Scaling of the processed samples based on chip temperature (temperature compensation) and calibration
coefficients.
The CE program RAM (CE PRAM) is loaded at boot time by the MPU and then executed by the CE. Each CE instruction word
is 2 bytes long. The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code
pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the
multiplexer cycle ends (see System Timing Summary in the Functional Description Section).
The CE data RAM (CE DRAM) can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR, RTM, and MPU, respectively, such that memory accesses to CE_RAM do not collide. Holding re-
gisters are used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed,
depending on the frequency of CKMPU.
Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE.
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Name
IA
VA
IB
VB
IC
VC
TEMP
V3
Zero
Reference
V3P3
V3P3
V3P3
V3P3
V3P3
V3P3
VBIAS
VBIAS
Description
Phase A current
Phase A voltage
Phase B current
Phase B voltage
Phase C current
Phase C voltage
Temperature
V3 monitor
Table 2: CE DRAM Locations for ADC Results
Meter Equations
The Compute Engine (CE) program for industrial meter configurations implements the equations in Table 3. The I/O RAM
register EQU specifies the equation to be used based on the number and arrangement of phases used for metering. In case of
single and two-phase metering, the unconnected inputs should be tied to V3P3A, the analog supply voltage. The EQU
selection enables the 71M6513 to calculate polyphase power measurement based on the type of service used. Table 3 also
states the sequence of the multiplexer in the AFE.
Page: 12 of 104
© 2005-2011 Teridian Semiconductor Corporation

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