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AP0100CS Schematic ( PDF Datasheet ) - Aptina

Teilenummer AP0100CS
Beschreibung High-Dynamic Range (HDR) Image Signal Processor
Hersteller Aptina
Logo Aptina Logo 




Gesamt 30 Seiten
AP0100CS Datasheet, Funktion
Aptina Confidential and Proprietary
Preliminary
AP0100CS HDR: Image Signal Processor (ISP)
Features
AP0100CS High-Dynamic Range (HDR) Image Signal
Processor (ISP)
AP0100CS Data Sheet
For the latest product data sheet revision, refer to Aptina’s Web site:www.aptina.com
Features
• Up to 1.2Mp (1280x960) Aptina sensor support
• 45 fps at 1.2Mp, 60 fps at 720p
• Optimized for operation with HDR sensors.
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz auto
flicker detection and avoidance
• Adaptive Local Tone Mapping (ALTM)
• Programmable Spatial Transform Engine (STE).
• Pre-rendered Graphical Overlay
• Two-wire serial programming interface (CCIS)
• Interface to low-cost Flash or EEPROM through SPI
bus (to configure and load patches, etc.)
• High-level host command interface
• Standalone operation supported
• Up to 5 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
• Integrated video encoder for NTSC/PAL with overlay
capability and 10-bit I-DAC
Applications
• IP cam and CCTV - HD
• Enables CCTV -HD w/ MP sensor
Ordering Information
Table 1:
Available Part Numbers
Part Number
AP0100CSSL00APGA0-E
AP0100CSSL00APGA0
AP0100CSSL00APGAD-E
AP0100CSSL00APGAH-E
Description
100-ball VFBGA Package Part Samples
100-ball VFBGA Package Part
AP0100CS demo kit
AP0100CS headboard
Table 2:
Key Performance Parameters
Parameter
Primary camera
interfaces
Primary camera input
Output interface
Output format
Maximum resolution
NTSC output
PAL output
Input clock range
Supply voltage
Operating temp.
Power consumption
Value
Parallel and HiSPi
RAW12 Linear/RAW12, RAW14 (HiSPi
format only) Companded
Analog composite, up to 16-bit parallel
digital output
YUV422 8-bit,10-bit, and 10-, 12-bit
tone-mapped Bayer
1280x960 (1.2Mp)
720H x 487V
720H x 576V
6-30 MHz
VDDIO_S
1.8 or 2.8V nominal
VDDIO_H
2.5 or 3.3V nominal
VDD_REG
1.8V nominal
VDD 1.2V nominal
VDD_PLL
1.2V nominal
VDD_DAC
1.2V nominal
VDDIO_OTPM 2.5 or 3.3V nominal
VDDA_DAC
3.3V nominal
VDD_PHY
2.8V nominal
–30°C to +70°C
170 mW
PDF: 5895261839 / Source: 7801027569
AP0100CS_DS - Rev. B Pub. 8/12 EN
1 Aptina reserves the right to change products or specifications without notice.
©2012 Aptina Imaging Corporation All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Aptina without
notice. Products are only warranted by Aptina to meet Aptina’s production data sheet specifications.






AP0100CS Datasheet, Funktion
Aptina Confidential and Proprietary
Preliminary
AP0100CS HDR: Image Signal Processor (ISP)
General Description
General Description
Aptina's AP0100CS is a high-performance, ultra-low power in-line, digital image
processor optimized for use with HDR (High Dynamic Range) sensors. The AP0100CS
provides full auto-functions support (AWB and AE) and ALTM (Adaptive Local Tone
Mapping) to enhance HDR images and advanced noise reduction which enables excel-
lent low-light performance.
Functional Overview
Figure 1 shows the typical configuration of the AP0100CS in a camera system. On the
host side, a two-wire serial interface is used to control the operation of the AP0100CS,
and image data is transferred using the analog or parallel interface between the
AP0100CS and the host. The AP0100CS interface to the sensor also uses a parallel inter-
face.
Figure 1:
AP0100CS Connectivity
1.2Mp HDR Sensor
or 12-bit parallel
Two-lane HiSPi
Two-wire serial I/F (CCIM)
Analog
NTSC/PAL display
Two-wire serial IF (CCIS)
Host
System Interfaces
Figure 2: “Typical Parallel Configuration,” on page 7 and Figure 3: “Typical HiSPi Config-
uration,” on page 8 show typical AP0100CS device connections.
All power supply rails must be decoupled from ground using capacitors as close as
possible to the package.
The AP0100CS signals to the sensor and host interfaces can be at different supply voltage
levels to optimize power consumption and maximize flexibility. Table 1 on page 9
provides the signal descriptions for the AP0100CS.
PDF: 5895261839 / Source: 7801027569
AP0100CS_DS - Rev. B Pub. 8/12 EN
6 Aptina reserves the right to change products or specifications without notice.
©2012 Aptina Imaging Corporation All rights reserved.

6 Page









AP0100CS pdf, datenblatt
Table 4:
Package Pinout
12
A DOUT[11] DOUT[13]
B DOUT[12] DOUT[10]
C DOUT[9] DOUT[8]
D DOUT[5] DOUT[6]
E DOUT[2] DOUT[3]
F DOUT[0] DOUT[1]
G
GND
VDD_PLL
H VDD_PLL VDD_PLL
J EXT_REG RESET_BAR
K
GND
FB_SENSE
34
PIXCLK_OUT LV_OUT
5
GPIO_2
DOUT[14]
FV_OUT
GPIO_3
DOUT[15]
GPIO[1]
GPIO_4
DOUT[7]
VDDIO_H
VDDIO_HOST
DOUT[4]
VDDIO_H
GND
EXTCLK
VDDIO_H
GND
XTAL
VDD
VDD
LDO_OUTPUT VDDIO_OTPM DAC_NEG
VDD_REG
VDD_DAC
DAC_POS
ENLDO
GND
VDDA_DAC
6
TRST_BAR
GPIO[5]
SPI_CS_BAR
VDD
GND
GND
VDD
DAC_REF
DATA0_P
DATA0_N
7
SPI_SDI
8
SADDR
SPI_SCLK
SDATA
SPI_SDO
VDDIO_H
FRAME_SYNC VDD
GND
LV_IN
GND
VDDIO_S
GND
DIN[6]
GNDA_DAC VDD_PHY
CLK_P
DATA1_N
CLK_N
DATA1_P
9
SCLK
10
STANDBY
TRIGGER_OUT RESET_BAR_OUT
M_SDATA
M_SCLK
FV_IN
MCLK_OUT
PIXCLK_IN
DIN[11]
DIN[9]
DIN[10]
DIN[7]
DIN[8]
DIN[4]
DIN[5]
DIN[0]
DIN[2]
DIN[1]
DIN[3]

12 Page





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