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74VHC02PW Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 74VHC02PW
Beschreibung Quad 2-input NOR gate
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 14 Seiten
74VHC02PW Datasheet, Funktion
74VHC02; 74VHCT02
Quad 2-input NOR gate
Rev. 01 — 13 August 2009
Product data sheet
1. General description
The 74VHC02; 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7-A.
The 74VHC02; 74VHCT02 provide a quad 2-input NOR function.
2. Features
I Balanced propagation delays
I All inputs have a Schmitt-trigger action
I Inputs accept voltages higher than VCC
I Input levels:
N The 74VHC02 operates with CMOS input level
N The 74VHCT02 operates with TTL input level
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74VHC02D
40 °C to +125 °C SO14
74VHCT02D
74VHC02PW 40 °C to +125 °C TSSOP14
74VHCT02PW
74VHC02BQ
40 °C to +125 °C DHVQFN14
74VHCT02BQ
Description
plastic small outline package; 14 leads;
body width 3.9 mm
Version
SOT108-1
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm






74VHC02PW Datasheet, Funktion
NXP Semiconductors
74VHC02; 74VHCT02
Quad 2-input NOR gate
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
25 °C
40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74VHCT02
VIH HIGH-level VCC = 4.5 V to 5.5 V
input voltage
2.0 - - 2.0
-
2.0
-V
VIL LOW-level VCC = 4.5 V to 5.5 V
input voltage
- - 0.8 -
0.8
-
0.8 V
VOH
VOL
II
ICC
ICC
CI
HIGH-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 50 µA
IO = 8.0 mA
LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 50 µA
IO = 8.0 mA
input leakage VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
additional
per input pin;
supply current VI = VCC 2.1 V;
other pins at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
input
capacitance
4.4
3.94
-
-
-
-
-
-
4.5
-
0
-
-
-
-
3
-
-
0.1
0.36
0.1
2.0
1.35
10
4.4
3.80
-
-
-
-
-
-
-
-
0.1
0.44
1.0
20
1.5
10
4.4
3.70
-
-
-
-
-
-
-V
-V
0.1 V
0.55 V
2.0 µA
40 µA
1.5 mA
10 pF
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions
25 °C
40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ[1] Max Min
Max
Min
Max
74VHC02
tpd propagation nA, nB to nY; see Figure 6 [2]
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
- 3.9 7.9 1.0 9.5 1.0 10.0 ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
- 5.5 11.4 1.0 13 1.0 14.5 ns
CL = 15 pF
- 2.9 5.5 1.0
6.5
1.0
7.0 ns
CL = 50 pF
4.2 7.5 1.0
8.5
1.0
9.5 ns
CPD power
CL = 50 pF; fi = 1 MHz;
[3] -
7.0 -
-
-
-
- pF
dissipation VI = GND to VCC
capacitance
74VHC_VHCT02_1
Product data sheet
Rev. 01 — 13 August 2009
© NXP B.V. 2009. All rights reserved.
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74VHC02PW pdf, datenblatt
NXP Semiconductors
74VHC02; 74VHCT02
Quad 2-input NOR gate
13. Abbreviations
Table 10. Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
Low-power Schottky Transistor-Transistor Logic
MM Machine Model
14. Revision history
Table 11. Revision history
Document ID
Release date
74VHC_VHCT02_1 20090813
Data sheet status
Product data sheet
Change notice
-
Supersedes
-
74VHC_VHCT02_1
Product data sheet
Rev. 01 — 13 August 2009
© NXP B.V. 2009. All rights reserved.
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