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PDF 74VHCT02 Data sheet ( Hoja de datos )
| Número de pieza | 74VHCT02 | |
| Descripción | Quad 2-input NOR gate | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74VHC02; 74VHCT02
Quad 2-input NOR gate
Rev. 01 — 13 August 2009
Product data sheet
1. General description
The 74VHC02; 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7-A.
The 74VHC02; 74VHCT02 provide a quad 2-input NOR function.
2. Features
I Balanced propagation delays
I All inputs have a Schmitt-trigger action
I Inputs accept voltages higher than VCC
I Input levels:
N The 74VHC02 operates with CMOS input level
N The 74VHCT02 operates with TTL input level
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74VHC02D
−40 °C to +125 °C SO14
74VHCT02D
74VHC02PW −40 °C to +125 °C TSSOP14
74VHCT02PW
74VHC02BQ
−40 °C to +125 °C DHVQFN14
74VHCT02BQ
Description
plastic small outline package; 14 leads;
body width 3.9 mm
Version
SOT108-1
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
1 page  
NXP Semiconductors
74VHC02; 74VHCT02
Quad 2-input NOR gate
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74VHC02
VIH HIGH-level VCC = 2.0 V
input voltage VCC = 3.0 V
1.5 - - 1.5
-
1.5
-V
2.1 - - 2.1
-
2.1
-V
VCC = 5.5 V
3.85 -
- 3.85
-
3.85
-V
VIL
LOW-level
VCC = 2.0 V
input voltage VCC = 3.0 V
- - 0.5 -
0.5
-
0.5 V
- - 0.9 -
0.9
-
0.9 V
VCC = 5.5 V
- - 1.65 -
1.65
-
1.65 V
VOH HIGH-level VI = VIH or VIL
output voltage IO = −50 µA; VCC = 2.0 V
1.9 2.0
-
1.9
-
1.9
-V
IO = −50 µA; VCC = 3.0 V 2.9 3.0 -
2.9
-
2.9
-V
IO = −50 µA; VCC = 4.5 V 4.4 4.5 -
4.4
-
4.4
-V
IO = −4.0 mA; VCC = 3.0 V 2.58 -
- 2.48
-
2.40
-V
IO = −8.0 mA; VCC = 4.5 V 3.94 -
- 3.80
-
3.70
-V
VOL
LOW-level
VI = VIH or VIL
output voltage IO = 50 µA; VCC = 2.0 V
- 0 0.1 -
0.1
-
0.1 V
IO = 50 µA; VCC = 3.0 V
- 0 0.1 -
0.1
-
0.1 V
IO = 50 µA; VCC = 4.5 V
- 0 0.1 -
0.1
-
0.1 V
IO = 4.0 mA; VCC = 3.0 V - - 0.36 -
0.44
-
0.55 V
IO = 8.0 mA; VCC = 4.5 V - - 0.36 -
0.44
-
0.55 V
II input leakage VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
- - 0.1 -
1.0
-
2.0 µA
ICC supply current VI = VCC or GND; IO = 0 A; - - 2.0 -
20
-
40 µA
VCC = 5.5 V
CI input
capacitance
- 3 10 -
10
-
10 pF
74VHC_VHCT02_1
Product data sheet
Rev. 01 — 13 August 2009
© NXP B.V. 2009. All rights reserved.
5 of 14
5 Page 
NXP Semiconductors
74VHC02; 74VHCT02
Quad 2-input NOR gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
D BA
terminal 1
index area
A
A1
E
c
detail X
terminal 1
index area
L
e
2
1
Eh
14
e1
b
6
vM C AB
wM C
7
e
8
y1 C
C
y
13 9
Dh
0 2.5
5 mm
X
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c D(1) Dh E(1) Eh e e1 L
v
w
y y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1 1.65
2.9 1.35
2.6 1.15
2.4 0.85
0.5
2
0.5
0.3
0.1 0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
EUROPEAN
PROJECTION
SOT762-1
---
MO-241
---
ISSUE DATE
02-10-17
03-01-27
Fig 10. Package outline SOT762-1 (DHVQFN14)
74VHC_VHCT02_1
Product data sheet
Rev. 01 — 13 August 2009
© NXP B.V. 2009. All rights reserved.
11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet 74VHCT02.PDF ] | |
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