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PDF HCPL-0710 Data sheet ( Hoja de datos )
| Número de pieza | HCPL-0710 | |
| Descripción | 40 ns Propagation Delay / CMOS Optocoupler | |
| Fabricantes | Avago | |
| Logotipo |  |
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HCPL-7710/0710
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-7710 or HCPL-0710 optocouplers
utilize the latest CMOS IC technology to achieve outstand-
ing performance with very low power consumption. The
HCPL-x710 require only two bypass capacitors for complete
CMOS compatibility.
• +5 V CMOS compatibility
• 8 ns maximum pulse width distortion
• 20 ns maximum prop. delay skew
• High speed: 12 Mbd
• 40 ns maximum prop. delay
Basic building blocks of the HCPL-x710 are a CMOS LED
driver IC, a high speed LED and a CMOS detector IC. A
• 10 kV/µs minimum common mode rejection
• -40°C to 100°C temperature range
CMOS logic input signal controls the LED driver IC, which
supplies current to the LED. The detector IC incorporates
an integrated photodiode, a high-speed transimpedance
amplifier, and a voltage comparator with an output driver.
• Safety and regulatory approvals
UL Recognized
3750 Vrms for 1 min. per UL 1577
5000 Vrms for 1 min. per UL 1577 (for HCPL-7710
option 020)
CSA Component Acceptance Notice #5
Functional Diagram
IEC/EN/DIN EN 60747-5-5
**VDD1 1
8 VDD2**
TRUT–HVTIOARBML=E630 Vpeak for HCPL-7710 Option 060
(POSIT–IVVEIOLROMG=IC5)67 Vpeak for HCPL-0710 Option 060
VI, INPUT LED1 VO, OUTPUT
VI 2
7 NC*
H
L
ApplOiOcFaNtFions
H
L
• Digital fieldbus isolation: DeviceNet, SDS, Profibus
NC* 3
GND1 4
LED1
SHIELD
IO
6 VO
5 GND2
• AC plasma display panel level shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
* Pin 3 is the anode of the internal LED and must be left
unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally.
** A 0.1 µF bypass capacitor must be connected
between pins 1 and 4, and 5 and 8.
8 VDD2**
7 NC*
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
IO
6 VO
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
5 GND2
1 page  
Insulation and Safety Related Specifications
Value
Parameter
Symbol 7710 0710 Units
Minimum External Air
L(I01) 7.1
4.9 mm
Gap (Clearance)
Minimum External
L(I02) 7.4
4.8 mm
Tracking (Creepage)
Minimum Internal Plastic
0.08 0.08 mm
Gap (Internal Clearance)
Tracking Resistance
CTI
(Comparative Tracking Index)
≥175 ≥175 V
Isolation Group
IIIa IIIa
Conditions
Measured from input terminals to output
terminals, shortest distance through air.
Measured from input terminals to output
terminals, shortest distance path along body.
Insulation thickness between emitter and
detector; also known as distance through
insulation.
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the equip-
ment designer when determining the circuit insulation
requirements. However, once mounted on a printed circuit
board, minimum creepage and clearance requirements
must be met as specified for individual equipment stan-
dards. For creepage, the shortest distance path along the
surface of a printed circuit board between the solder fillets
of the input and output leads must be considered. There
are recommended techniques such as grooves and ribs,
which may be used on a printed circuit board to achieve
desired creepage and clearances. Creepage and clearance
distances will also change depending on factors such as
pollution degree and insulation level.
5
5 Page 
Pulse-width distortion (PWD) is the difference between
tPHL and tPLH and often determines the maxim um data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by
the minimum pulse width (in ns) being transm itted.
Typically, PWD on the order of 20 - 30% of the minimum
pulse width is tolerable. The PWD specification for the
HCPL-x710 is 8 ns (10%) maximum across recommend-
ed operating conditions. 10% maximum is dictated
by the most stringent of the three fieldbus standards,
PROFIBUS.
Propagation delay skew, tPSK, is an important parameter
to consider in parallel data applications where synchro-
nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of op-
tocouplers, differences in propagation delays will cause
the data to arrive at the outputs of the optocouplers at
different times. If this difference in propagation delay
is large enough it will determine the maximum rate at
which parallel data can be sent through the optocou-
plers.
Propagation delay skew is defined as the differ-
ence between the minimum and maximum propa
gation delays, either tPLH or tPHL, for any given group
of optocouplers that are operating under the same
conditions (i.e., the same drive current, supply volta ge,
output load, and operating temperature). As illustrated
in Figure 15,if the inputs of a group of optocouplers
are switched either ON or OFF at the same time, tPSK is
the difference between the shortest propagation delay,
either tPLH or tPHL, and the longest propagation delay,
either tPLH or tPHL.
As mentioned earlier, tPSK can determine the maximum
parallel data transmission rate. Figure 16 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the opto-
couplers. The figure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case, the
data is assumed to be clocked off of the rising edge of
the clock.
VI 50%
VO
2.5 V,
CMOS
tPSK
VI 50%
VO
Figure 15. Propagation delay skew waveform
2.5 V,
CMOS
DATA
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
tPSK
tPSK
Figure 16. Parallel data transmission example
Propagation delay skew represents the uncertain-
ty of where an edge might be after being sent
through an optocoupler. Figure 16 shows that there
will be uncertainty in both the data and clock lines.
These two areas of uncertainty must not overlap;
otherwise, the clock signal might arrive before all of
the data outputs have settled, or some of the data
outputs may start to change before the clock signal
has arrived. From these considerations, the absolute
minimum pulse width that can be sent through op-
tocouplers in a parallel application is twice tPSK.
A cautious design should use a slightly longer pulse
width to ensure that any additional uncertainty in the
rest of the circuit does not cause a problem.
The HCPL-x710 optocouplers offer the advantage of
guaranteed specifications for propagation delays,
pulse-width distortion, and propagation delay skew
over the recommended temperature, and power supply
ranges.
11
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| PDF Descargar | [ Datasheet HCPL-0710.PDF ] | |
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