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Z2V56S40BTP Schematic ( PDF Datasheet ) - Mezza

Teilenummer Z2V56S40BTP
Beschreibung 256Mb Synchronous DRAM
Hersteller Mezza
Logo Mezza Logo 




Gesamt 30 Seiten
Z2V56S40BTP Datasheet, Funktion
北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://www.echip.com.cn
256Mb Synchronous DRAM Specification
Z2V56S20BTP
Z2V56S30BTP
Z2V56S40BTP
Deutron Electronics Corp.
8F, 68, SEC. 3, NANKING E. RD., TAIPEI 104,
TAIWAN, R. O. C.
TEL : 886-2-2517-7768
FAX : 886-2-2517-4575
http: // www.deutron.com.tw






Z2V56S40BTP Datasheet, Funktion
256Mb Synchronous DRAM北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://www.echip.com.cn
Z2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT)
Z2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT)
Z2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
PIN FUNCTION
CLK
Input
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-12
Input
Master Clock:
All other inputs are referenced to the rising edge of CLK
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
Chip Select:
When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-12.
The Column Address is specified by A0-9,11(x4)/A0-9(x8)/A0-8(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
BA0,1
Input
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
Input / Output Data In and Data out are referenced to the rising edge of CLK.
DQM(x4,x8),
DQMU/L(x16)
Input
Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Vdd, Vss
VddQ, VssQ
Power Supply Power Supply for the memory array and peripheral circuitry.
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
Jan.2004
Page -4
Rev.1.1

6 Page









Z2V56S40BTP pdf, datenblatt
256Mb Synchronous DRAM北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://www.echip.com.cn
Z2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT)
Z2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT)
Z2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
H X X XX
L H H HX
L H H LX
RE- L H L X BA, CA, A10
FRESHING
L
L
H
H BA, RA
L L H L BA, A10
L L L HX
Op-Code,
LLLL
Mode-Add
H X X XX
L H H HX
L H H LX
MODE
L H L X BA, CA, A10
REGISTER
L
L
H
H BA, RA
SETTING
L L H L BA, A10
L L L HX
Op-Code,
LLLL
Mode-Add
Command
Action
DESEL NOP (Idle after tRC)
NOP
NOP (Idle after tRC)
TBST
ILLEGAL
READ / WRITE ILLEGAL
ACT
ILLEGAL
PRE / PREA ILLEGAL
REFA
ILLEGAL
MRS
ILLEGAL
DESEL NOP (Idle after tRSC)
NOP
NOP (Idle after tRSC)
TBST
ILLEGAL
READ / WRITE ILLEGAL
ACT
ILLEGAL
PRE / PREA ILLEGAL
REFA
ILLEGAL
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
Jan.2004
Page -10
Rev.1.1

12 Page





SeitenGesamt 30 Seiten
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