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Número de pieza | Z2V56S30BTP | |
Descripción | 256Mb Synchronous DRAM | |
Fabricantes | Mezza | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de Z2V56S30BTP (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! 北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://www.echip.com.cn
256Mb Synchronous DRAM Specification
Z2V56S20BTP
Z2V56S30BTP
Z2V56S40BTP
Deutron Electronics Corp.
8F, 68, SEC. 3, NANKING E. RD., TAIPEI 104,
TAIWAN, R. O. C.
TEL : 886-2-2517-7768
FAX : 886-2-2517-4575
http: // www.deutron.com.tw
1 page 256Mb Synchronous DRAM北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://www.echip.com.cn
Z2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT)
Z2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT)
Z2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
BLOCK DIAGRAM
DQ0-7
I/O Buffer
Memory Array
8192x1024x8
Cell Array
Bank #0
Memory Array
8192x1024x8
Cell Array
Bank #1
Memory Array
8192x1024x8
Cell Array
Bank #2
Memory Array
8192x1024x8
Cell Array
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Clock Buffer
Control Signal Buffer
A0-12 BA0,1
CLK CKE
/CS /RAS
/CAS
/WE DQM
Note:This figure shows the Z2V56S30BTP
The Z2V56S20BTP configuration is 8192x2048x4 of cell array and DQ0-3
The Z2V56S40BTP configuration is 8192x512x16 of cell array and DQ0-15
Type Designation Code
Z2 V 56 S 3 0 B TP-G7
Access Item
-6 : 6ns ( 166MHz/3-3-3)
-7 : 7 ns (143MHz/3-3-3)
-75 : 7.5ns ( 133MHz/3-3-3)
-8 : 8 ns (100MHz/2-2-2)
Package Type
Process Generation
Function
Organization
Synchronous DRAM
Density
Interface
MIRA DRAM
TP : TSOP(II); G: Pb Free
B : 3rd generation
0 : Random Column
2 : x4, 3 : x8, 4: x16
56 :256Mbit
V :LVTTL
Jan.2004
Page- 3
Rev.1.1
5 Page 256Mb Synchronous DRAM北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://www.echip.com.cn
Z2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT)
Z2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT)
Z2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State
PRE -
CHARGING
/CS
H
L
L
L
L
L
L
L
ROW
ACTIVATING
H
L
L
L
L
L
L
L
WRITE RE-
COVERING
H
L
L
L
L
L
L
L
/RAS /CAS /WE Address
X X XX
H H HX
H H LX
H L X BA, CA, A10
L H H BA, RA
L H L BA, A10
L L HX
Op-Code,
LLL
Mode-Add
X X XX
H H HX
H H LX
H L X BA, CA, A10
L H H BA, RA
L H L BA, A10
L L HX
Op-Code,
LLL
Mode-Add
X X XX
H H HX
H H LX
H L X BA, CA, A10
L H H BA, RA
L H L BA, A10
L L HX
Op-Code,
LLL
Mode-Add
Command
Action
DESEL NOP (Idle after tRP)
NOP
NOP (Idle after tRP)
TBST
ILLEGAL*2
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA NOP*4 (Idle after tRP)
REFA
ILLEGAL
MRS
ILLEGAL
DESEL NOP (Row Active after tRCD)
NOP
NOP (Row Active after tRCD)
TBST
ILLEGAL*2
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
DESEL NOP
NOP
NOP
TBST
ILLEGAL*2
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
Jan.2004
Page -9
Rev.1.1
11 Page |
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