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5100 Schematic ( Datenblatt PDF ) - Intel

Teilenummer 5100
Beschreibung Memory Controller Hub Chipset
Hersteller Intel
Logo Intel Logo 

Gesamt 30 Seiten
		
5100 Datasheet, Funktion
Intel® 5100 Memory Controller Hub
Chipset
Datasheet
July 2009
Revision 005US
Order Number: 318378-005US






5100 Datasheet, Funktion
Intel® 5100 MCH Chipset—Contents
3.8.12.13HDRLOG2[7:2,0] - Header Log 2 ............................................... 163
3.8.12.14HDRLOG3[7:2,0] - Header Log 3 ............................................... 164
3.8.12.15RPERRCMD[7:2,0] - Root Port Error Command ............................ 164
3.8.12.16RPERRSTS[7:2,0] - Root Error Status Register ............................ 164
3.8.12.17RPERRSID[7:2,0] - Error Source Identification Register ................ 165
3.8.12.18SCSPCAPID[7:2,0] - Intel® 5100 Memory Controller Hub Chipset-
specific Capability ID ............................................................... 166
3.8.12.19PEX_ERR_DOCMD[7:2,0] - PCI Express* Error Do Command Register .
166
3.8.12.20EMASK_UNCOR_PEX[0] - Uncorrectable Error Detect Mask For ESI 167
3.8.12.21EMASK_UNCOR_PEX[7:2] - Uncorrectable Error Detect Mask ........ 167
3.8.12.22EMASK_COR_PEX[7:2,0] - Correctable Error Detect Mask ............. 168
3.8.12.23EMASK_RP_PEX[7:2,0] - Root Port Error Detect Mask .................. 168
3.8.12.24PEX_FAT_FERR[7:2,0] - PCI Express* First Fatal Error Register ..... 169
3.8.12.25PEX_NF_COR_FERR[7:2,0] - PCI Express* First Non-Fatal or
Correctable Error Register ........................................................ 169
3.8.12.26PEX_FAT_NERR[7:2,0] - PCI Express* Next Fatal Error Register .... 170
3.8.12.27PEX_NF_COR_NERR[7:2,0] - PCI Express* Non Fatal or Correctable
Next Error Register.................................................................. 171
3.8.12.28PEX_UNIT_FERR[7:2] - PCI Express* First Unit Error Register ....... 172
3.8.12.29PEX_UNIT_NERR[7:2] - PCI Express* Next Unit Error Register ...... 172
3.8.13 Error Registers ..................................................................................... 172
3.8.13.1 FERR_GLOBAL - Global First Error Register ................................. 173
3.8.13.2 NERR_GLOBAL - Global Next Error Register ................................ 174
3.8.13.3 FERR_FAT_FSB[1:0]: FSB First Fatal Error Register...................... 175
3.8.13.4 FERR_NF_FSB[1:0]: FSB First Non-Fatal Error Register ................ 176
3.8.13.5 NERR_FAT_FSB[1:0]: FSB Next Fatal Error Register..................... 176
3.8.13.6 NERR_NF_FSB[1:0]: FSB Next Non-Fatal Error Register ............... 176
3.8.13.7 NRECFSB[1:0]: Non Recoverable FSB Error Log Register .............. 176
3.8.13.8 RECFSB[1:0]: Recoverable FSB Error Log Register ....................... 177
3.8.13.9 NRECADDRL[1:0]: Non Recoverable FSB Address Low Error Log
Register ................................................................................. 177
3.8.13.10NRECADDRH[1:0]: Non Recoverable FSB Address High Error Log
Register ................................................................................. 177
3.8.13.11EMASK_FSB[1:0]: FSB Error Mask Register ................................ 178
3.8.13.12ERR2_FSB[1:0]: FSB Error 2 Mask Register ................................ 178
3.8.13.13ERR1_FSB[1:0]: FSB Error 1 Mask Register ................................ 178
3.8.13.14ERR0_FSB[1:0]: FSB Error 0 Mask Register ................................ 179
3.8.13.15MCERR_FSB[1:0]: FSB MCERR Mask Register.............................. 179
3.8.13.16FERR_FAT_INT - Internal First Fatal Error Register....................... 180
3.8.13.17FERR_NF_INT - Internal First Non-Fatal Error Register ................. 180
3.8.13.18NERR_FAT_INT - Internal Next Fatal Error Register ...................... 180
3.8.13.19NERR_NF_INT - Internal Next Non-Fatal Error Register................. 181
3.8.13.20NRECINT - Non Recoverable Internal Intel® 5100 Memory Controller
Hub Chipset Error Log Register ................................................. 181
3.8.13.21EMASK_INT - Internal Error Mask Register.................................. 181
3.8.13.22ERR2_INT - Internal Error 2 Mask Register ................................. 182
3.8.13.23ERR1_INT - Internal Error 1 Mask Register ................................. 182
3.8.13.24ERR0_INT - Internal Error 0 Mask Register ................................. 183
3.8.13.25MCERR_INT - Internal MCERR Mask Register............................... 183
3.9 Memory Control Registers ................................................................................. 183
3.9.1 General Registers ................................................................................. 183
3.9.1.1 MC - Memory Control Settings................................................... 183
3.9.1.2 MCA - Memory Control Settings A .............................................. 185
3.9.1.3 MS: Memory Status Register..................................................... 185
3.9.1.4 MCDEF3: MCDEF Register 3 ...................................................... 186
3.9.1.5 ERRPER: Error Period Prescaler ................................................. 186
3.9.1.6 MTR[1:0][5:0] - Memory Technology Registers ........................... 187
3.9.1.7 DMIR[1:0][4:0] - DIMM Interleave Range................................... 188
Intel® 5100 Memory Controller Hub Chipset
Datasheet
6
July 2009
Order Number: 318378-005US

6 Page







5100 pdf, datenblatt
Intel® 5100 MCH Chipset—Contents
5.17
5.18
5.19
5.20
5.16.2 Using DMA ........................................................................................... 326
5.16.3 Interrupt Handling ................................................................................ 327
5.16.3.1 Interrupt Service Routine (ISR) ................................................. 327
5.16.3.2 DMA Engine Interrupt Handler................................................... 328
5.16.3.3 Channel Interrupt Callback ....................................................... 328
DMA Engine Driver........................................................................................... 329
5.17.1 Stream/Port Arbitration ......................................................................... 330
5.17.1.1 Level 3 - IOU0, IOU1, DMA Arbitration ....................................... 330
5.17.2 Supported PCI Express* Transactions ...................................................... 331
5.17.2.1 Unsupported Messages ............................................................ 333
5.17.2.2 32/64-bit Addressing ............................................................... 333
5.17.3 Transaction Descriptor........................................................................... 333
5.17.3.1 Transaction ID ........................................................................ 333
5.17.3.2 Attributes ............................................................................... 333
5.17.3.3 Traffic Class............................................................................ 334
5.17.4 Transaction Behavior............................................................................. 334
5.17.4.1 Inbound Transactions .............................................................. 334
5.17.4.2 Inbound Read/Write Streaming ................................................. 335
5.17.4.3 Zero-Length Reads/Writes ........................................................ 335
5.17.4.4 Inbound Write Transactions ...................................................... 335
5.17.4.5 PHOLD Support ....................................................................... 336
5.17.4.6 Interrupt Handling ................................................................... 336
5.17.4.7 Error Messages ....................................................................... 337
5.17.4.8 Inbound Vendor-Specific Messages ............................................ 337
5.17.4.9 Outbound Transactions ............................................................ 337
5.17.4.10Outbound Non-Posted Transactions ........................................... 337
5.17.4.11Outbound Vendor-Specific Messages .......................................... 337
5.17.4.12Lock Support .......................................................................... 338
5.17.4.13Peer-to-peer Transactions ........................................................ 338
5.17.4.14Peer-to-peer Configuration Cycles ............................................. 338
5.17.5 Ordering Rules ..................................................................................... 339
5.17.5.1 Inbound Transaction Ordering Rules .......................................... 339
5.17.5.2 Outbound Transaction Ordering Rules ........................................ 340
5.17.5.3 MCH Ordering Implementation .................................................. 340
5.17.5.4 Interrupt Ordering Rules .......................................................... 341
5.17.6 Prefetching Policies ............................................................................... 341
5.17.7 PCI Express* Hide Bit............................................................................ 341
5.17.8 No Isochronous Support ........................................................................ 341
5.17.9 PCI Hot Plug*....................................................................................... 342
Power Management.......................................................................................... 342
5.18.1 Supported ACPI States .......................................................................... 342
System Reset.................................................................................................. 342
5.19.1 Intel® 5100 Memory Controller Hub Chipset Reset Types ........................... 343
5.19.1.1 Power-Good Mechanism ........................................................... 343
5.19.1.2 Hard Reset Mechanism ............................................................. 344
5.19.1.3 Processor-Only Reset Mechanism............................................... 344
5.19.1.4 Targeted Reset Mechanism ....................................................... 344
5.19.1.5 BINIT# Mechanism .................................................................. 345
5.19.2 Intel® 5100 Memory Controller Hub Chipset Power Sequencing................... 345
5.19.3 Reset Sequencing ................................................................................. 346
SMBus Interfaces Description ............................................................................ 347
5.20.1 Internal Access Mechanism .................................................................... 348
5.20.2 SMBus and PCI Express* Interoperability Timeout Recommendation ............ 348
5.20.3 SMBus Transaction Field Definitions......................................................... 349
5.20.3.1 Command Field ....................................................................... 349
5.20.3.2 Byte Count Field...................................................................... 350
5.20.3.3 Address Byte 3 Field ................................................................ 350
Intel® 5100 Memory Controller Hub Chipset
Datasheet
12
July 2009
Order Number: 318378-005US

12 Page


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