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TC58BVG0S3HTAI0 Schematic ( PDF Datasheet ) - Toshiba

Teilenummer TC58BVG0S3HTAI0
Beschreibung 1 GBIT (128M x 8-BIT) CMOS NAND E2PROM
Hersteller Toshiba
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Gesamt 30 Seiten
TC58BVG0S3HTAI0 Datasheet, Funktion
TC58BVG0S3HTAI0
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1 GBIT (128M × 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TC58BVG0S3HTAI0 is a single 3.3V 1 Gbit (1,107,296,256 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 1024blocks.
The device has a 2112-byte static register which allows program and read data to be transferred between the
register and the memory cell array in 2112-bytes increments. The Erase operation is implemented in a single block
unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
The TC58BVG0S3HTAI0 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
The TC58BVG0S3HTAI0 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected
internally.
FEATURES
Organization
x8
Memory cell array 2112 × 64K × 8
Register
2112× 8
Page size
2112 bytes
Block size
(128K + 4K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
ECC Status Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 1004 blocks
Max 1024 blocks
Power supply
VCC = 2.7V to 3.6V
Access time
Cell array to register 40 µs typ.
Serial Read Cycle
25 ns min (CL=50pF)
Program/Erase time
Auto Page Program
Auto Block Erase
330 µs/page typ.
2.5 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
50 µA max
Package
TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
8bit ECC for each 528Bytes is implemented on a chip.
1 2012-08-31C






TC58BVG0S3HTAI0 Datasheet, Funktion
AC TEST CONDITIONS
PARAMETER
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
TC58BVG0S3HTAI0
CONDITION
VCC: 2.7 to 3.6V
Vcc-0.2V, 0.2V
3 ns
Vcc / 2
Vcc / 2
CL (50 pF) + 1 TTL
Note: Busy to ready time depends on the pull-up resistor tied to the RY / BY pin.
(Refer to Application Note (9) toward the end of this document.)
PROGRAMMING / ERASING / READING CHARACTERISTICS
(Ta = -40 to 85 , VCC = 2.7 to 3.6V)
SYMBOL
PARAMETER
MIN TYP.
tPROG
Average Programming Time
N Number of Partial Program Cycles in the Same Page
tBERASE
Block Erasing Time
tR Memory Cell Array to Starting Address
(1) Refer to Application Note (12) toward the end of this document.
330
2.5
40
MAX
700
4
5
120
UNIT NOTES
µs
(1)
ms
µs
Data Output
When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend on tRHOH
(25ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on
tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling
edge of /WE, and waveforms look like Extended Data Output Mode.
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TC58BVG0S3HTAI0 pdf, datenblatt
Column Address Change in Read Cycle Timing Diagram (1/2)
CLE
CE
tCLS tCLH
tCS tCH
WE
tWC
tCLS tCLH
tCS tCH
TC58BVG0S3HTAI0
tCLR
tCLR
ALE
RE
I/O
RY / BY
tALH tALS
tALH tALS
tR
tDS tDH
tDS tDH tDS tDH tDS tDH tDS tDH
tWB
tDS tDH
00h
CA0 CA8 PA0 PA8
to 7 to 11 to 7 to 15
30h
Page address
P
tRC
tREA
70h
Status
Output
00h
DOUT DOUT DOUT
A A + 1 A +N
Page address
P
Column
address A
1
Continues from 1 of next page
12 2012-08-31C

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