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NB3F8L3010C Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NB3F8L3010C
Beschreibung 3.3V / 2.5V / 1.8V / 1.5V 3:1:10 LVCMOS Fanout Buffer
Hersteller ON Semiconductor
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Gesamt 13 Seiten
NB3F8L3010C Datasheet, Funktion
NB3F8L3010C
3.3V / 2.5V / 1.8V / 1.5V
3:1:10 LVCMOS Fanout Buffer
Description
The NB3F8L3010C is a 3:1:10 Clock / Data fanout buffer operating
on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V /
1.5 V VDDOn supplies which must be equal or less than VDD.
A Mux selects between a Crystal input, or either of two
differential/SE Clock / Data inputs. Differential Inputs accept
LVPECL, LVDS, HCSL, or SSTL and Single−Ended levels. The
MUX control lines, SEL0 and SEL1, select CLK0/CLK0,
CLK1/CLK1, or Crystal input pins per Table 3. The Crystal input is
disabled when a Clock input is selected. Output enable pin, OE,
synchronously forces a High Impedance state (HZ) when Low per
Table 4.
Outputs consist of 10 single−ended LVCMOS outputs.
Features
Ten CMOS / LVTTL Outputs up to 200 MHz
Differential Inputs Accept LVPECL, LVDS, HCSL, or SSTL
Crystal Oscillator Interface
Crystal Input Frequency Range: 10 MHz to 50 MHz
Output Skew: 10 ps Typical
Additive RMS Phase Jitter @ 125 MHz, (12 kHz – 20 MHz): 0.03 ps
(Typical)
Synchronous Output Enable
Output Defined Level When Input is Floating
Power Supply Modes:
Single 3.3 V
Single 2.5 V
Mixed 3.3 V ± 5% Core/2.5 V ± 5% Output Operating Supply
Mixed 3.3 V ± 5% Core/1.8 V ± 0.2 V Output Operating Supply
Mixed 3.3 V ± 5% Core/1.5 V ± 0.15 V Output Operating Supply
Mixed 2.5 V ± 5% Core/ 1.8 V ± 0.2 V Output Operating Supply
Mixed 2.5 V ± 5% Core /1.5 V ± 0.15 V Output Operating Supply
Two Separate Output Bank Power Supplies
Industrial temp. range -40°C to 85°C
These are Pb−Free Devices
Applications
Clock Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure
End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
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1 32
QFN32
G SUFFIX
CASE 488AM
MARKING
DIAGRAM
1
NB3F8L
3010C
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information page 12 of this
data sheet.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 7
1
Publication Order Number:
NB3F8L3010C/D






NB3F8L3010C Datasheet, Funktion
NB3F8L3010C
Table 11. AC CHARACTERISTICS VDD = 3.3 V ± 5% (3.135 V to 3.465 V) or VDD = 2.5 V ±5% (2.375 V to 2.625 V) and
VDDOn = 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ± 0.15 V (1.35 V
to 1.65 V); TA = −40°C to 85°C
Symbol
Parameter
Test Conditions
Min Typ Max Unit
tsk(o)
tJITTERF
tR / tF
odc
tEN
Output Skew (Notes 6 and 7)
Additive RMS
Phase Jitter
(Integrated
12 kHz *
20 MHz)
(Note 8)
Input clock from
CLK0/CLK0 or
CLK1/CLK1
External clock
over drives
crystal interface
Input clock from
crystal
Output Rise/Fall Time (20% and 80%)
Output Duty Cycle
Output Enable
Time (Note 9)
OE
VDDOn = 3.3 V ± 5%
VDDOn = 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
VDDOn = 3.3 V ± 5%
VDDOn = 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
VDDOn = 3.3 V ± 5%
VDDOn = 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
VDDOn = 3.3 V ± 5%
VDDOn = 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
VDDOn = 3.3 V ± 5%
VDDOn = 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
10 55 ps
0.03 ps
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
150 350 500
ps
150 350 500
150 350 600
150 350 600
45 55 %
40 60
40 60
40 60
4 cycles
tDIS
Output Disable
OE
Time (Note 9)
4 cycles
MUX_ISOLATION MUX_ISOLATION
155.52 MHz
55
dB
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
5. XTAL_IN can be overdriven relative to a signal a crystal would provide.
6. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOn/2.
7. This parameter is defined in accordance with JEDEC Standard 65.
8. See phase noise plot.
9. These parameters are guaranteed by characterization. Not tested in production. See Parameter Measurement Information
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6

6 Page









NB3F8L3010C pdf, datenblatt
NB3F8L3010C
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the
package and the electrical performance, a land pattern must
be incorporated on the Printed Circuit Board (PCB) within
the footprint of the package corresponding to the exposed
metal pad or exposed heat slug on the package, as shown in
Figure 14. The solderable area on the PCB, as defined by the
solder mask, should be at least the same size/shape as the
exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should
be designed on the PCB between the outer edges of the land
pattern and the inner edges of pad pattern for the leads to
avoid any shorts. While the land pattern on the PCB provides
a means of heat transfer and electrical grounding from the
package to the board through a solder joint, thermal vias are
necessary to effectively conduct from the surface of the PCB
to the ground plane(s). The land pattern must be connected
to ground through these vias. The vias act as “heat pipes”.
The number of vias (i.e. “heat pipes”) is application specific
and dependent upon the package power dissipation as well
as electrical conductivity requirements. Thus, thermal and
electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias
is incorporated in the land pattern. It is recommended to use
as many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13 mils
(0.30 to 0.33 mm) with 1 oz copper via barrel plating. This
is desirable to avoid any solder wicking inside the via during
the soldering process which may result in voids in solder
between the exposed pad/slug and the thermal land.
Precautions should be taken to eliminate any solder voids
between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only.
Figure 14. Suggested Assembly for Exposed Pad Thermal Release Path – Cut−away View (not to scale)
ORDERING INFORMATION
Device
Package
Shipping
NB3F8L3010CMNG
QFN32
(Pb−Free)
74 Units / Rail
NB3F8L3010CMNR4G
QFN32
(Pb−Free)
1000 / Tape & Reel
NB3F8L3010CMNTWG
QFN32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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