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NB3L83948C Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NB3L83948C
Beschreibung 2.5V / 3.3V Differential and LVTTL/LVCMOS 2:1 MUX to 1:12 LVCMOS Fanout
Hersteller ON Semiconductor
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Gesamt 7 Seiten
NB3L83948C Datasheet, Funktion
NB3L83948C
2.5 V / 3.3 V Differential and
LVTTL/LVCMOS 2:1 MUX to
1:12 LVCMOS Fanout
Description
The NB3L83948C is a pure 2.5 V / 3.3 V (VDD = VDDO) or mixed
mode 3.3 V Core (VDD) / 2.5 V Output (VDDO) clock distribution
buffer with the capability to select either a differential LVPECL /
LVDS / LVHSTL / SSTL / HCSL or single ended LVCMOS / LVTTL
compatible input clock, such as a Primary or a Test Clock. All other
control inputs (CLK_SEL, CLK_EN, and OE) are LVTTL/LVCMOS
level compatible.
The NB3L83948C provides an enable input, CLK_EN pin, which
synchronously enables or disables the clock outputs while in the LOW
state. Since this input is internally synchronized to the input clock,
changing only when the input is LOW, potential output glitching or
runt pulse generation is eliminated.
The 12 LVCMOS output pins drive 50 W series or parallel
terminated transmission lines. The outputs can also be disabled to a
high impedance (tri−stated) via the OE input, or enabled when High.
Fit, Form, and Function compatible with ICS83948I−147,
ICS83948I−01, CY29948AXI, and MPC9448/9448L
Features
2.5 V / 3.3V (VDD = VDDO) or
3.3 V VDD / 2.5 V VDDO Operation:
2.5 $5%, 2.375 to 2.625 V
3.3 $5%; 3.135 to 3.465 V
350 MHz Clock Support
Accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL, or LVCMOS
Clock Inputs
LVCMOS Compatible Control Inputs
12 LVCMOS Clock Outputs
Synchronous Clock Select
Output Enable to High Z State Control
100 ps Max. Skew Between Outputs
Industrial Temp. Range −40°C to +85°C
32−pin LQFP Package
These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAMS*
LQFP−32
FA SUFFIX
CASE 873A
NB3L
83948C
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(*Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VDDO
VDD
GND
Q0
Q1
CLK_EN
LVCMOS_CLK
CLK
CLK
CLK_SEL
D
Q
1
2
Q2
Q3
Q4
Q5
Q6
VDDO
Q7
Q8
Q9
Q10
Q11
OE
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 2
1
Publication Order Number:
NB3L83948C/D






NB3L83948C Datasheet, Funktion
CLK
CLK
VDDO
2
NB3L83948C
VPP = VIH − VIL
VDDO
2
LVCMOS_CLK
VDDO
2
VDDO
2
VIHCMR
GND
VDDO
VDDO
Qx 2 2
tPHL
tPHL
VDDO tPW VDDO VDDO
2 22
Qx
tP
tSKEWDC % + ǒtPWńtPǓ 100
Figure 4. AC Reference Measurement
NB3L83948C
Qx
ZO = 50 W
50 W
D Receiver /
Scope
DUT
GND
Figure 5. Typical Termination for Output Driver and Device Evaluation. Supplies may be centered on GND
($1.65 V or $1.25 V) to permit direct connection into 50 W to GND Scope modules
ORDERING INFORMATION
Device
Package
Shipping
NB3L83948CFAG
LQFP−32
(Pb−Free)
250 Units / Tray
NB3L83948CFAR2G
LQFP−32
(Pb−Free)
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
6

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