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PDF STD25P03L Data sheet ( Hoja de datos )
| Número de pieza | STD25P03L | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NTD25P03L, STD25P03L
Power MOSFET
−25 A, −30 V, Logic Level P−Channel DPAK
Designed for low voltage, high speed switching applications and to
withstand high energy in the avalanche and commutation modes.
The source−to−drain diode recovery time is comparable to a discrete
fast recovery diode.
Features
• S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
• Bridge Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp ≤ 10 ms)
Drain Current
− Continuous @ TA = 25°C
− Single Pulse (tp ≤ 10 ms)
Total Power Dissipation @ TA = 25°C
Operating and Storage Temperature Range
VDSS
VGS
VGSM
ID
IDM
PD
TJ, Tstg
−30
±15
±20
−25
−75
75
−55 to
+150
V
V
Vpk
A
Apk
W
°C
Single Pulse Drain−to−Source Avalanche
EAS 200 mJ
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc,
Peak IL = 20 Apk, L = 1.0 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
RqJC
RqJA
RqJA
°C/W
1.65
67
120
Maximum Lead Temperature for Soldering
Purposes, (1/8 in from case for 10 seconds)
TL
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
http://onsemi.com
V(BR)DSS
−30 V
RDS(on) Typ
51 mW @ 5.0 V
D
ID Max
−25 A
P−Channel
G
S
4
12
3
DPAK
CASE 369C
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
1
Gate
2
Drain
3
Source
A
Y
WW
25P03L
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 5
1
Publication Order Number:
NTD25P03L/D
1 page  
NTD25P03L, STD25P03L
10
8 −VDS
QT
30
25
6
Q1
4
20
Q2 −VGS 15
10
2 ID = −25 A 5
TJ = 25°C
0 Q3
0
0 2.5 5 7.5 10 12.5 15
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
1000
100
VDD = −15 V
ID = −25 A
VGS = −5.0 V
TJ = 25°C
10
tr
tf
td(off)
td(on)
1
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
25
VGS = 0 V
20 TJ = 25°C
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
15
10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
http://onsemi.com
5
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| PDF Descargar | [ Datasheet STD25P03L.PDF ] | |
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