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PDF AR2316 Data sheet ( Hoja de datos )
| Número de pieza | AR2316 | |
| Descripción | Single Chip MAC/Baseband/Radio and Processor | |
| Fabricantes | Atheros | |
| Logotipo |  |
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Data Sheet
PRELIMINARY
May 2005
AR2316 Single Chip MAC/Baseband/Radio and Processor
for 2.4 GHz Wireless LANs
General Description
The Atheros AR2316 integrated the MAC/
baseband/radio and processor into a single
chip for wireless access point and router
applications. It includes a 2.4 GHz radio, MIPS
4000 processor, 802.11 MAC/baseband
processor, 802.3 Ethernet MAC and MII
interface, SDRAM controller, external memory
interface for Flash, ROM, or RAM, PCI bus
interface or a flexible local bus, UART, GPIOs,
LED controls.
The AR2316 implements an 802.11 MAC/
baseband processor supporting all IEEE
802.11g data rates (1 to 54 Mbps) and all IEEE
802.11b complementary key coding (CCK) data
rates (1 to 11 Mbps). In Atheros Super G™
mode, AR2316 supports data rates up to 108
Mbps. Additional features include forward
error correction coding at rates for
1/2, 2/3, and 3/4, signal detection, automatic
gain control, frequency offset estimation,
symbol timing, channel estimation, error
recovery, enhanced security, and quality of
service (QoS). The AR2316 performs receive
and transmit filtering for IEEE 802.3 and 802.11
networks.
The AR2316 is an all CMOS, highly integrated
single-chip solution that supports 802.11b/g
WLANs.
Features
■ Integrated MIPS 4000 processor
■ 180 MHz processor frequency
■ IEEE 802.11b/g Access Point, Ad Hoc, and
station functions supported
■ OFDM and CCK modulation schemes
supported
■ Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36,
48, 54 Mbps and Atheros Super G™ mode
offering up to 108 Mbps
■ IEEE 802.3 Ethernet MAC supporting 10/
100 Mbps, full and half duplex, and MII
interface to external Ethernet PHY
■ UART for console support
■ Flexible, programmable local bus
■ PCI bus host and client modes
■ IEEE 1149.1 standard test access port and
boundary scan architecture supported
■ EJTAG based debugging of the processor
core supported
■ Standard 0.18 µm CMOS technology
■ 15 mm x 15 mm 233 PBGA package
System Block Diagram
RF RF
Filter Switch
Receiver
Frequency
Synthesizer
Transmitter
Bias/Control
Controls
SDRAM
Controller
and Memory
Interface
ADC
MIPS
Processor
DAC
AR2316
Baseband(PHY)
and Wireless
MAC
Ethernet MAC
Fast UART
Local Bus
Peripheral
Interface
Flash
SDRAM Interface
MII Interface
40 MHz
Crystal
Serial Interface
Parallel Interface
LED Controls
GPIOs
© 2000-2005 by Atheros Communications, Inc. All rights reserved. Atheros™, 5-UP™, Driving the Wireless Future™, Atheros Driven™, Atheros Turbo
Mode™, and the Air is Cleaner at 5-GHz™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of
Atheros Communications, Inc. All other trademarks are the property of their respective holders.
Subject to change without notice.
COMPANY CONFIDENTIAL
•1
1 page  
(PCI_HIMR) 65
3.5.15 Host Interrupt Enable Register
(PCI_HIER) 66
3.5.16 PCI Tx Chain Enable
(PCI_PTxE) 66
3.5.17 PCI Tx Chain Disable
(PCI_PTxD) 66
3.5.18 PCI Tx Descriptor Pointer
(PCI_PTxDP) 67
3.5.19 PCI Rx Chain Enable
(PCI_PRxE) 67
3.5.20 PCI Rx Chain Disable
(PCI_PRxD) 67
3.5.21 PCI Rx Descriptor Pointer
(PCI_PRxDP) 67
3.5.22 Reset Control (PCI_RC) 68
3.5.23 Sleep Control (PCI_SCR) 68
3.5.24 PCI Clock Domain Interrupt
Pending (PCI_INTPEND) 69
3.5.25 Sleep Force (PCI_SFR) 69
3.5.26 PCI Clock Domain Configura-
tion/Status (PCI_CFG) 69
3.5.27 Silicon Revision (PCI_SREV) 71
3.5.28 Sleep Enable Alias
(PCI_SLE) 71
3.5.29 TxE Write Posting
(PCI_TxEPOST) 72
3.5.30 QCU Sleep Mask
(PCI_QSM) 72
3.5.31 PCI Debug 0 (PCI_DBG_0) 72
3.5.32 Sleep Performance Counter 0
Read-Only Alias
(PCI_SPC_ROA_0) 73
3.5.33 Sleep performance Counter 1
Read-Only Alias
(PCI_SPC_ROA_1) 73
3.5.34 CIS Tuples 73
3.6 SPI Flash Interface Registers 74
3.6.1 SPI Control/Status (SPI_CS) 74
3.6.2 SPI Address/Opcode
(SPI_AO) 75
3.6.3 SPI Data (SPI_D) 75
3.6.4 SPI Register Notes 75
4 Package Dimensions 77
5 Ordering Information 79
Atheros Communications, Inc.
WLANs • 5
AR2316 MAC/BB/Radio and Processor for 2.4 GHz
5 Page 
PRELIMINARY
Table 1-3. PCI Signal to Pin Relationships and Descriptions
Signal Name
PCI_CBE3_L
PCI_CBE2_L
PCI_CBE1_L
PCI_CBE0_L
PCI_CLKRUN_L
PCI_DEVSEL_L
PCI_EPRM_EN_L
PCI_FRAME_L
PCI_GNT1_L
PCI_GNT0_L
PCI_IDSEL
PCI_INT_L
PCI_IRDY_L
PCI_PAR
PCI_PERR_L
PCI_REQ1_L
PCI_REQ0_L
PCI_RST_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
Pin Direction
Description
P13 I/O PCI multiplexed bus command and byte
C9
I/O
enables. During the address phase of a
transaction, these signals define the bus
A2 I/O command. During the data phase, they are used
as byte enables.
H2 I/O
B6 I Provides for starting and stopping the PCI clock.
B3 I/O PCI device select.
D11
C7 I/O PCI frame.
R8 I PCI grant.
T5 I
T16 I PCI ID select.
T3 O PCI interrupt.
C8 I/O PCI initiator ready.
L14 I/O PCI parity.
C4 I/O PCI parity error.
P6 O PCI request.
U4 O
U3 I PCI Reset
B5 I/O PCI system error.
D5 I/O PCI stop.
D6 I/O PCI target ready.
Table 1-4. Local Bus Signal-to-Pin Relationships
Signal Name
Local Bus
LB_ADDR_0
LB_ADDR_1
LB_ADDR_2
LB_ADDR_3
LB_CS
LB_DATA_15
LB_DATA_14
LB_DATA_13
LB_DATA_12
LB_DATA_11
LB_DATA_10
LB_DATA_9
LB_DATA_8
LB_DATA_7
LB_DATA_6
Pin Direction
J2 I Address [0]
T1 I Address [1]
P2 I Address [2]
U16 I Address [3]
U4 I Chip select
L14 I/O Data [15]
J16 I/O Data [14]
C7 I/O Data [13]
C8 I/O Data [12]
B8 I/O Data [11]
C5 I/O Data [10]
D5 I/O Data [9]
C3 I/O Data [8]
C4 I/O Data [7]
B5 I/O Data [6]
Description
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR2316 MAC/BB/Radio and Processor for 2.4 GHz WLANs • 11
May 2005 • 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AR2316.PDF ] | |
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