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FE1.1S Schematic ( PDF Datasheet ) - JFD

Teilenummer FE1.1S
Beschreibung USB 2.0 HIGH SPEED 4-PORT HUB CONTROLLER
Hersteller JFD
Logo JFD Logo 




Gesamt 10 Seiten
FE1.1S Datasheet, Funktion
USB 2.0 4-Port Hub
Data Sheet Rev. 1.0
www.jfd-ic.com
FE1.1S
USB 2.0 HIGH SPEED 4-PORT HUB CONTROLLER
_______________________Data Sheet_______________________
INTRODUCTION
The FE1.1s is a highly integrated, high quality,
high performance, low power consumption, yet
low cost solution for USB 2.0 High Speed 4-Port
Hub.
It adopts Single Transaction Translator (STT)
architecture to be more cost effective. Six,
instead of two, non-periodic transaction buffers
are used to minimize potential traffic jamming.
The whole design is based on state-machine-
control to reduce the response delay time; no
micro controller is used in this chip.
To guarantee high quality, the whole chip is
covered by Test Scan Chain – even on the high
speed (480MHz) modules, so that all the logic
components could be fully tested before shipping.
Special Build-In-Self-Test mode is designed to
exercise all high, full, and low speed Analog
Front End (AFE) components on the packaging
and testing stages as well.
Low power consumption is achieved by using
0.1m technology and comprehensive
power/clock control mechanism. Most part of the
chip will not be clocked unless needed.
FEATURES
Fully compliant with Universal Serial Bus
Specification Revision 2.0 (USB 2.0);
Upstream facing port supports High-
Speed (480MHz) and Full-Speed
(12MHz) modes;
4 downstream facing ports support
High-Speed (480MHz), Full-Speed
(12MHz), and Low-Speed (1.5MHz)
modes;
Integrated USB 2.0 Transceivers;
Integrated upstream 1.5KΩ pull-up,
downstream 15KΩ pull-down, and serial
resisters;
Integrated 5V to 3.3V and 1.8V regulator.
Integrated Power-On-Reset circuit;
Integrated 12MHz Oscillator with feedback
resister, and crystal load capacitance;
Integrated 12MHz-to-480MHz Phase Lock
Loop (PLL);
Single Transaction Translator (STT) –
One TT for all downstream ports;
The TT could handle 64 periodic Start-
Split transactions, 32 periodic
Complete-Split transactions, and 6
none-periodic transactions;
Automatic self-power status monitoring;
Automatic re-enumeration when Self-
NOV. 29, 2008
Subject to Change Without Notice
1






FE1.1S Datasheet, Funktion
USB 2.0 4-Port Hub
Data Sheet Rev. 1.0
LED1/ 43 23 I/O Port 1 and Port 3 Enabled Indicator (LED) Control, and
1
EESCL
external Serial EEPROM Clock.
LED2
44 24 I/O Port 2 and Port 4 Enabled Indicator (LED) Control
1
PWRJ 47 25 O Downstream Device Power Enable, active low, for Ganged
Power Switching.
OVCJ
48 26 I Over Current Indicator, active low, for Global Over-Current
Protection.
TESTJ/
2
27 I/O Test Mode Enable, active low with internal pull-up, and
1
EESDA
external Serial EEPROM Data/Address.
VD18
9
28 P 1.8V power input.
Type Abbreviation –
I : Input; O : Output; I/O : Input/Output; P : Power/Ground; UT: USB Transceiver.
TESTJ
LED1
FE1.1s
LED2
DRV
Green Port 1 Indicator
Green
Port 3 Indicator
Green Port 2 Indicator
Green
Port 4 Indicator
Hub Active/Suspend Indicator
SDA
SCL
EEPROM
A0
A1
A2
Fig. 3: LED and EEPROM Connections
Note 1 – LED Status Indicators and External Serial EEPROM Interface
The FE1.1s supports up to 5 LED for status indication with DRV, LED1, and LED2 pins, as shown by
Fig. 4. For each Downstream Facing Port, one LED (Green) is provided to indicate that the attached
device of the corresponding port is enabled or not. The fifth LED (Red) shows the Active (On) or
Suspend (Off) status of the Hub itself. The FE1.1s can be configured by an external serial EEPROM
via LED1 and TESTJ pins. The EEPROM is checked and loaded each time after chip reset.
NOV. 29, 2008
Subject to Change Without Notice
6

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