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PDF TLC555 Data sheet ( Hoja de datos )
| Número de pieza | TLC555 | |
| Descripción | CMOS General Purpose Timer | |
| Fabricantes | Chips Winner | |
| Logotipo |  |
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1. TLC555  Hay una vista previa y un enlace de descarga de TLC555 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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TLC555
CMOS General Purpose Timer
DESCRIPTION
PIN CONFIGURATION
The TLC555 is a highly stable controller capable of producing
accurate timing pulses. With a monostable operation, the time
D,P PACKAGE
delay is controlled by one external resistor and one capacitor.
GND 1
8 VCC
With an astable operation, the frequency and duty cycle are
TRIG 2
7 DISCH
accurately controlled by two external resistors and one capacitor.
OUT 3
6 THRES
This CMOS RC timers improved parameters include low supply
current, wide operating supply voltage range, low THRES, TRIG
and RESET currents, no crow barring of the supply current
during output transitions, higher frequency performance and no
requirement to decouple CONT for stable operation.
RESET 4
5 CONT
(Top View)
FEATURES
Exact equivalent in most cases for SE/NE555
Low supply current
High speed operation is 500 kHz guaranteed
Wide operation supply voltage range is 2 to 18 volts
Timing from microseconds through hours
Operates in both astable and monostable modes
Adjustable duty cycle
High output source/sink driver can drive TTL/CMOS
APPLICATION
Precision Timing
Pulse Generation
Time Delay Generation
Sequential Timing
Pulse width modulation
Missing Pulse Detector
ORDERING INFORMATION
Temperature Range
-40°C to +85°C
Package
DIP-8L
SOP-8L
Pb-Free
Orderable
Device
TLC555P
TLC555D
Package Qty
50Units/Tube
100Units/Tube
June.2007
Rev 1.1
1
1 page  
TLC555
PIN FUNCTION DESCRIPTION
No. Name
Description
1 GND Circuit ground pin.
This trigger pin is the input to the comparator B and is used to set the latch,
which in turn causes the output to go high. This is the beginning of the timing
2 TRIG sequence in monostable operation. Triggering is accomplished by taking the pin
from above to below a voltage level of 1/3 Vcc. The action of the TRIG pin is
level-sensitive, allowing slow rate-of-change waveforms, as well as pulses, to
be used as trigger sources.
The state of the output pin will always reflect the inverse of the logic state of
the latch. This relationship may be best explained in terms of latch-input trigger
conditions. To trigger the output to a high condition, the TRIG pin is momen-
3 OUT tarily taken from a higher to a lower level. The output can be returned to a low
state by causing the THRES pin to go from a lower to a higher level, which
resets the latch. The output can also be made to go low by taking the RESET
pin to a low state near ground.
4
RESET
This reset pin is also used to reset the latch and return the output to a low
state.
This control voltage pin allows direct access to the 2/3 Vcc voltage-divider
point, the reference level for the comparator A. It also allows indirect access to
5 CONT the comparator B, as there is a 2:1 divider from this point to the comparator B
reference input. Use of this terminal is the option of the user, but it does allow
extreme flexibility by permitting modification of the timing period, resetting of
the comparator, etc.
This is one input to the comparator A and is used to reset the latch, which
6 THRES causes the OUT pin to go low. Resetting via this terminal is accomplished by
taking the terminal from below to above a voltage level of 2/3 Vcc. The action
of the THRES pin is level sensitive, allowing slow rate-of-change waveforms.
This pin is low resistance to ground when the OUT pin is low, and is high
7 DISCH resistance to ground when the OUT pin is high. Usually the timing capacitor is
connected between DISCH pin and ground, and is discharged when it effec-
tively shorted to ground.
8 VCC Positive supply voltage
June.2007
Rev 1.1
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet TLC555.PDF ] | |
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