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PDF Si7317DN Data sheet ( Hoja de datos )

Número de pieza Si7317DN
Descripción P-Channel 150 V (D-S) MOSFET
Fabricantes Vishay 
Logotipo Vishay Logotipo



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No Preview Available ! Si7317DN Hoja de datos, Descripción, Manual

P-Channel 150 V (D-S) MOSFET
Si7317DN
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
- 150
RDS(on) () Max.
1.2 at VGS = - 10 V
1.3 at VGS = - 6 V
ID (A)f
- 2.8
- 2.7
Qg (Typ.)
6.5 nC
PowerPAK 1212-8
FEATURES
• TrenchFET® Power MOSFETs
• PowerPAK® Package
- Low Thermal Resistance
• 100 % Rg and UIS Tested
• Material categorization:
For definitions of compliance please see
www.vishay.com/doc?99912
Available
3.3 mm
S
1S
3.3 mm
2
S
3G
4
D
8D
7
D
6
D
5
Bottom View
Ordering Information:
Si7317DN-T1-GE3 (Lead (Pb)-free and Halogen-free)
APPLICATIONS
• Active Clamp circiuts in DC/DC
Power Supplies
• Load Switch
G
S
D
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Limit
Unit
Drain-Source Voltage
Gate-Source Voltage
VDS - 150
VGS
± 30
V
TC = 25 °C
- 2.8
Continuous Drain Current (TJ = 150 °C)a,b
TC = 70 °C
TA = 25 °C
ID
- 2.2
- 1.1a,b
Pulsed Drain Current (t = 100 µs)
TA = 70 °C
IDM
- 0.9a,b
-2
A
Continuous Source-Drain Diode Currenta,b
TC = 25 °C
TA = 25 °C
IS
- 8e
- 2.7a,b
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
L 0.1 mH
IAS
EAS
4
0.8
mJ
TC = 25 °C
19.8
Maximum Power Dissipationa,b
TC = 70 °C
TA = 25 °C
PD
12.7
3.2a,b
W
TA = 70 °C
2.1a,b
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)c,d
TJ, Tstg
- 55 to 150
260
°C
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 5 s.
c. See solder profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
d. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
e. Package limited.
f. Based on TC = 25 °C.
Document Number: 62892
For technical questions, contact: [email protected]
www.vishay.com
S13-1817-Rev. A, 12-Aug-13
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

1 page




Si7317DN pdf
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3.2
Si7317DN
Vishay Siliconix
2.4
1.6
0.8
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Max Current vs. Case Temperature
24 2.0
18 1.5
12 1.0
6 0.5
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Power Junction-to-Case
0.0
0
25 50 75 100 125
TA - Ambient Temperature (°C)
Power Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 62892
For technical questions, contact: [email protected]
www.vishay.com
S13-1817-Rev. A, 12-Aug-13
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

5 Page





Si7317DN arduino
AN822
Vishay Siliconix
105
Spreading Copper (sq. in.)
95
85
75
65
55
0%
45
100 %
50 %
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 5. Spreading Copper - Si7401DN
130
120 Spreading Copper (sq. in.)
110
100
90
80
50 %
100 %
70
60 0 %
50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 6. Spreading Copper - Junction-to-Ambient Performance
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK
1212-8 uses the same packaging technology and has
been shown to have the same level of thermal perfor-
mance while having a footprint that is more than 40 %
smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
The PowerPAK 1212-8 combines small size with attrac-
tive thermal characteristics. By minimizing the thermal
rise above the board temperature, PowerPAK simplifies
thermal design considerations, allows the device to run
cooler, keeps rDS(ON) low, and permits the device to
handle more current than a same- or larger-size MOS-
FET die in the standard TSSOP-8 or SO-8 packages.
www.vishay.com
4
Document Number 71681
03-Mar-06

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