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AR0141CS Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer AR0141CS
Beschreibung 1/4-Inch Digital Image Sensor
Hersteller ON Semiconductor
Logo ON Semiconductor Logo 




Gesamt 30 Seiten
AR0141CS Datasheet, Funktion
AR0141CS: 1/4-Inch Digital Image Sensor
Features
1/4-Inch Digital Image Sensor
AR0141CS Datasheet, Rev. 6
For the latest datasheet, please visit: www.onsemi.com
Features
• Superior low-light performance
• Latest 3.0 m pixel with ON Semiconductor
DR-Pix technology
• Linear range capture
• 1.0 Mp and 720p (16:9) images
• Support for external mechanical shutter
• Support for external LED or xenon flash
• On-chip phase-locked loop (PLL) oscillator
• Integrated position-based color and lens shading
correction
• Slave mode for precise frame-rate control
• Stereo/3D camera support
• Statistics engine
• Data interfaces: four-lane serial high-speed pixel
interface (HiSPi) differential signaling (SLVS and
HiVCM), or parallel
• Auto black level calibration
• High-speed context switching
• Temperature sensor
Applications
• Video surveillance
• Scanning
• Industrial
• Stereo vision
• 720p60 video applications
General Description
The ON Semiconductor AR0141CS is a 1/4-inch CMOS
digital image sensor with an active-pixel array of
1280Hx800V. It captures images in linear mode, with a
rolling-shutter readout. It includes sophisticated cam-
era functions such as in-pixel binning, windowing and
both video and single frame modes. It is designed for
low light scene performance. It is programmable
through a simple two-wire serial interface. The
AR0141CS produces extraordinarily clear, sharp digital
pictures, and its ability to capture both continuous
video and single frames makes it the perfect choice for
a wide range of applications, including surveillance
and HD video.
Table 1:
Key Parameters
Parameter
Typical Value
Optical format
1/4-inch
Active pixels
1280(H) x 800(V) (entire
array)
Pixel size
3.0 m x 3.0 m
Color filter array
RGB Bayer, Monochrome,
RGB-IR
Shutter type
Electronic rolling shutter
and GRR
Input clock range
6 – 50 MHz
Output clock maximum
148.5 Mp/s (4-lane HiSPi)
74.25 Mp/s (Parallel)
Output
Serial
Parallel
HiSPi, 12-bit
10-, 12-bit
Frame rate 720p
60 fps
Responsivity
4.0 V/lux-sec
SNRMAX
Max Dynamic range
41 dB
Up to 79 dB
I/O 1.8 or 2.8 V
Supply
voltage
Digital
Analog
1.8 V
2.8 V
HiSPi
0.3 V - 0.6 V, 1.7 V - 1.9 V
Power consumption (typical)
326 mW (Linear Mode
1280x720 60 fps)
Operating temperature (ambient) -TA –30°C to + 70° C
Package options
9x9mm 63-ball iBGA
AR0141CS/D Rev. 6, 4/16 EN
1 ©Semiconductor Components Industries, LLC 2016,






AR0141CS Datasheet, Funktion
AR0141CS: 1/4-Inch Digital Image Sensor
.Functional Overview
Figure 3:
Typical Configuration: Parallel Pixel Data Interface
Digital Digital
I/O core
power1 power1
PLL Analog Analog
power1 power1 power1
VDD_IO VDD
VDD_PLL VAA VAA_PIX
Master clock
(6-50 MHz)
From
Controller
EXTCLK
SADDR
SDATA
SCLK
TRIGGER
OE_BAR
RESET_BAR
TEST
DGND
VDD_IO
VDD
VDD_PLL
VAA
VAA_PIX
Digital
ground
DOUT [11:0]
PIXCLK
LINE_VALID
FRAME_VALID
FLASH
SHUTTER
AGND
To
controller
Analog
ground
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for
slower two-wire speed.
3. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output inter-
face is used.
4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on lay-
out and design considerations. Check the AR0141CS demo headboard schematics for circuit recom-
mendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-
pling with the digital power planes is minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
7. The EXTCLK input is limited to 6-50 MHz.
AR0141CS/D Rev. 6, 4/16 EN
6 ©Semiconductor Components Industries, LLC, 2016.

6 Page









AR0141CS pdf, datenblatt
AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Output Interfaces
Pixel Output Interfaces
Parallel Interface
Output Enable Control
The parallel pixel data interface uses these output-only signals:
• FRAME_VALID
• LINE_VALID
• PIXCLK
• DOUT[11:0]
The parallel pixel data interface is disabled by default at power up and after reset. It can
be enabled by programming R0x301A. Table 5 shows the recommended settings.
When the parallel pixel data interface is in use, the serial data output signals can be left
unconnected. Set reset_register [bit 12 (R0x301A[12] = 1)] to disable the serializer while
in parallel output mode.
When the parallel pixel data interface is enabled, its signals can be switched asynchro-
nously between the driven and High-Z under pin or register control, as shown in Table 4.
Table 4: Output Enable Control
OE_BAR Pin
Disabled
Disabled
1
X
0
Drive Pins R0x301A[6]
0
1
0
1
X
Description
Interface High-Z
Interface driven
Interface High-Z
Interface driven
Interface driven
Configuration of the Pixel Data Interface
Fields in R0x301A are used to configure the operation of the pixel data interface. The
supported combinations are shown in Table 5.
Table 5: Configuration of the Pixel Data Interface
Serializer Disable
R0x301 A[12]
0
1
Parallel Enable
R0x301 A[7]
0
1
Description
Power up default.
Serial pixel data interface and its clocks are enabled. Transitions to soft standby are
synchronized to the end of frames on the serial pixel data interface.
Parallel pixel data interface, sensor core data output. Serial pixel data interface and its
clocks disabled to save power. Transitions to soft standby are synchronized to the end of
frames in the parallel pixel data interface.
AR0141CS/D Rev. 6, 4/16 EN
12
©Semiconductor Components Industries, LLC, 2016.

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