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Teilenummer | 74VHC08 |
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Beschreibung | Quad 2-input AND gate | |
Hersteller | NXP Semiconductors | |
Logo | ||
Gesamt 14 Seiten 74VHC08; 74VHCT08
Quad 2-input AND gate
Rev. 01 — 30 June 2009
Product data sheet
1. General description
The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard JESD7-A.
The 74VHC08; 74VHCT08 provide the quad 2-input AND function.
2. Features
I Balanced propagation delays
I All inputs have a Schmitt-trigger action
I Inputs accepts voltages higher than VCC
I Input levels:
N The 74VHC08 operates with CMOS logic levels
N The 74VHCT08 operates with TTL logic levels
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74VHC08D
74VHCT08D
−40 °C to +125 °C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74VHC08PW
74VHCT08PW
−40 °C to +125 °C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74VHC08BQ
74VHCT08BQ
−40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1
NXP Semiconductors
74VHC08; 74VHCT08
Quad 2-input AND gate
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max Min
Max
Min
Max
For type 74VHC08
tpd propagation nA, nB to nY; see Figure 6 [2]
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
- 4.0 8.8 1.0 10.5 1.0
11.0 ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
- 5.6 12.3 1.0 14 1.0 15.5 ns
CL = 15 pF
- 3.0 5.9 1.0
7.0
1.0
7.5 ns
CL = 50 pF
4.2 7.9 1.0 9.0 1.0 10.0 ns
CPD power
CL = 50 pF; fi = 1 MHz;
[3] - 10.0 -
-
-
-
- pF
dissipation VI = GND to VCC
capacitance
For type 74VHCT08
tpd propagation nA, nB to nY; see Figure 6 [2]
delay
VCC = 4.5 V to 5.5 V
CL = 15 pF
- 3.2 6.9 1.0
8.0
1.0
9.0 ns
CL = 50 pF
- 4.2 7.9 1.0 9.0 1.0 10.0 ns
CPD power
CL = 50 pF; fi = 1 MHz;
[3] - 12.0 -
-
-
-
- pF
dissipation VI = GND to VCC
capacitance
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
74VHC_VHCT08_1
Product data sheet
Rev. 01 — 30 June 2009
© NXP B.V. 2009. All rights reserved.
6 of 14
6 Page NXP Semiconductors
74VHC08; 74VHCT08
Quad 2-input AND gate
13. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
LSTTL
Low-power Schottky Transistor-Transistor Logic
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM Machine Model
CDM
Charged Device Model
TTL Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
74VHC_VHCT08_1 20090630
Data sheet status
Product data sheet
Change notice
-
Supersedes
-
74VHC_VHCT08_1
Product data sheet
Rev. 01 — 30 June 2009
© NXP B.V. 2009. All rights reserved.
12 of 14
12 Page | ||
Seiten | Gesamt 14 Seiten | |
PDF Download | [ 74VHC08 Schematic.PDF ] |
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