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D780056 Schematic ( PDF Datasheet ) - NEC

Teilenummer D780056
Beschreibung UPD780056
Hersteller NEC
Logo NEC Logo 




Gesamt 30 Seiten
D780056 Datasheet, Funktion
User’s Manual
µPD780058, 780058Y Subseries
8-Bit Single-Chip Microcontrollers
µPD780053
µPD780053Y
µPD780054
µPD780054Y
µPD780055
µPD780055Y
µPD780056
µPD780056Y
µPD780058
µPD780058BY
µPD780058B µPD78F0058Y
µPD78F0058 µPD780053Y(A)
µPD780053(A) µPD780054Y(A)
µPD780054(A) µPD780055Y(A)
µPD780055(A) µPD780056Y(A)
µPD780056(A) µPD780058BY(A)
µPD780058B(A)
Document No. U12013EJ3V2UD00 (3rd edition)
Date Published February 2003 N CP (K)
Printed in Japan
1997, 2003






D780056 Datasheet, Funktion
Page
Throughout
pp. 31, 32, 38, 39
p. 40
pp. 41, 42, 48, 49
p. 50
p. 60
pp. 62, 63
p. 75
pp. 77, 78
p. 132
p. 149
p. 167
p. 168
p. 177
p. 185
pp. 201 to 204
p. 235
p. 242
p. 252
Major Revisions in This Edition (1/2)
Description
Deletion of following product
µPD780058Y
Addition of following products
µPD780058B, 780058BY, 780053(A), 780053Y(A), 780054(A), 780054Y(A), 780055(A),
780055Y(A), 780056(A), 780056Y(A), 780058B(A), 780058BY(A)
Deletion of following packages
• 80-pin plastic QFP (GC-3B9 type)
• 80-pin plastic TQFP (GK-BE9 type)
Addition of following package
• 80-pin plastic TQFP (GK-9EU type)
1.1 Features, 1.7 Outline of Functions
• Change of operating voltage range of A/D and D/A converters of µPD780058 and 78F0058
• Change of supply voltage of µPD78F0058
Addition of 1.9 Differences Between Standard Model and (A) Model
2.1 Features, 2.7 Outline of Functions
• Change of operating voltage range of A/D and D/A converters of µPD78F0058Y
• Change of supply voltage of µPD78F0058Y
Addition of 2.9 Differences Between Standard Model and (A) Model
Change of processing when A/D converter is not used in 3.2.11 AVREF0
Change of recommended connection of unused pins and connection of P60 to P63, AVREF1, and
VPP pins in Table 3-1 Pin I/O Circuit Types
Change of processing when A/D converter is not used in 4.2.11 AVREF0
Change of recommended connection of unused pins and connection of P60 to P63, AVREF1, and
VPP pins in Table 4-1 Pin I/O Circuit Types
Modification of Note 2 in 6.2.8 Port 6
Addition of note on feedback resistor to Figure 7-3 Processor Clock Control Register Format
Addition of Table 8-5 INTP1/TI01 Pin Valid Edge and CR00 Capture Trigger Valid Edge
Addition of Table 8-6 INTP0/TI00 Pin Valid Edge and CR01 Capture Trigger Valid Edge
Correction of note on valid edge of INTP0/TI00/P00 and INTP1/TI01/P01 pin in Figure 8-8
Format of External Interrupt Mode Register 0
Addition of Figure 8-17 Configuration of PPG Output
Addition of Figure 8-18 PPG Output Operation Timing
8.5 16-Bit Timer/Event Counter Operating Cautions
Addition of description on TI01/P01/INTP1 to (5) Valid edge setting
Addition of (c) One-shot pulse output function to (6) Re-trigger of one-shot pulse
Addition of (8) Conflict operation
Addition of (9) Timer operation
Addition of (10) Capture operation
Addition of (11) Compare operation
Addition of (12) Edge detection
Modification of note on changing count clock in Figure 10-2 Timer Clock Select Register 2
Format
Modification of note on changing count clock in Figure 11-2 Timer Clock Select Register 2
Format
Addition of note on rewriting TCL2 in Figure 13-2 Format of Timer Clock Select Register 2
6 User's Manual U12013EJ3V2UD

6 Page









D780056 pdf, datenblatt
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12 User's Manual U12013EJ3V2UD

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