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NB3N1900K Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NB3N1900K
Beschreibung 3.3V 100/133MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer
Hersteller ON Semiconductor
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Gesamt 21 Seiten
NB3N1900K Datasheet, Funktion
NB3N1900K
3.3V 100/133 MHz
Differential 1:19 HCSL
Clock ZDB/Fanout Buffer for
PCIe[
Description
The NB3N1900K differential clock buffers are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point−to−point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel® QuickPath Interconnect
(Intel QPI), PCIe Gen1, Gen2, Gen3. The NB3N1900K internal PLL is
optimized to support 100 MHz and 133 MHz frequency operation.
The NB3N1900K supports HCSL output levels.
Features
Fixed Feedback Path for Lowest Input−to−Output Delay
Eight Dedicated OE# Pins for Hardware Control of Outputs
PLL Bypass Configurable for PLL or Fanout Operation
Selectable PLL Bandwidth
Spread Spectrum Compatible: Tracks Input Clock Spreading for Low
EMI
SMBus Programmable Configurations
100 MHz and 133 MHz PLL Mode to Meet the Next Generation
PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter
2 Tri−Level Addresses Selection (Nine SMBUS Addresses)
Cycle−to−Cycle Jitter: < 50 ps
Output−to−Output Skew: < 65 ps
Input−to−Output Delay: Fixed at 0 ps
Input−to−Output Delay Variation: < 50 ps
Phase Jitter: PCIe Gen3 < 1 ps rms
Phase Jitter: QPI 9.6GB/s < 0.2 ps rms
QFN 72−pin Package, 10 mm x 10 mm
These are Pb−Free Devices
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MARKING
DIAGRAM*
1 72
QFN72
MN SUFFIX
CASE 485DK
1
NB3N
1900K
AWLYYWWG
NB3N1900K = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 4
1
Publication Order Number:
NB3N1900K/D






NB3N1900K Datasheet, Funktion
Table 7. PIN DESCRIPTION
Pin #
Pin Name
38 DIF7
39 DIF7#
40 OE7#
41 DIF8
42 DIF8#
43 OE8#
44 GND
45 VDD
46 DIF9
47 DIF9#
48 OE9#
49 DIF10
50 DIF10#
51 OE10#
52 DIF11
53 DIF11#
54 OE11#
55 DIF12
56 DIF12#
57 OE12#
58 VDD
59 DIF13
60 DIF13#
61 DIF14
62 DIF14#
63 GND
64 DIF15
65 DIF15#
66 DIF16
67 DIF16#
68 VDD
69 DIF17
70 DIF17#
71 DIF18
72 DIF18#
NB3N1900K
Pin Type
Description
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
IN
Active low input for enabling DIF pair 7.
1 = disable outputs, 0 = enable outputs
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
IN
Active low input for enabling DIF pair 8.
1 = disable outputs, 0 = enable outputs
PWR Ground pin.
PWR Power supply, nominal 3.3 V
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
IN
Active low input for enabling DIF pair 9.
1 = disable outputs, 0 = enable outputs
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
IN
Active low input for enabling DIF pair 10.
1 = disable outputs, 0 = enable outputs
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
IN
Active low input for enabling DIF pair 11.
1 = disable outputs, 0 = enable outputs
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
IN
Active low input for enabling DIF pair 12.
1 = disable outputs, 0 = enable outputs
PWR Power supply, nominal 3.3 V
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
PWR Ground pin.
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
PWR Power supply, nominal 3.3 V
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
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NB3N1900K pdf, datenblatt
NB3N1900K
Table 15. CLOCK PERIODS − DIFFERENTIAL OUTPUTS WITH SPREAD SPECTRUM DISABLED
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
1us 1 Clock
−SSC
− ppm
−c2c jitter Short−Term Long−Term
Center AbsPer Average Average
SSC OFF Freq. MHz Min
Min
Min
0 ppm
Period
Nominal
+ ppm Long−
Term Average
Max
+SSC
+c2c jitter
Short−Term AbsPer
Average Max Max
Unit Notes
100.00 9.94900
DIF
133.33 7.44925
9.99900 10.00000
7.49925 7.50000
10.00100
7.50075
10.05100
7.55075
ns
37,
38, 39
ns
37,
38, 40
37. Guaranteed by design and characterization, not tested in production.
38. All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+ accuracy
requirements (±100 ppm). The 9ZX21901 itself does not contribute to ppm error.
39. Driven by SRC output of main clock, 100.00 MHz PLL Mode or Bypass mode
40. Driven by CPU output of main clock, 133.33 MHz PLL Mode or Bypass mode
Table 16. CLOCK PERIODS − DIFFERENTIAL OUTPUTS WITH SPREAD SPECTRUM ENABLED
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
1us 1 Clock
SSC ON
−SSC
− ppm
−c2c jitter Short−Term Long−Term
Center AbsPer Average Average
Freq. MHz Min
Min
Min
0 ppm
Period
Nominal
+ ppm
Long−Term
Average Max
+SSC
+c2c jitter
Short−Term AbsPer
Average Max Max
Unit Notes
99.75 9.94906 9.99906 10.02406 10.02506
10.02607
DIF
133.00 7.44930 7.49930 7.51805 7.51880
7.51955
10.05107
7.53830
10.10107
7.58830
ns
41,
42, 43
ns
41,
42, 44
41. Guaranteed by design and characterization, not tested in production.
42. All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+ accuracy
requirements (±100 ppm). The 9ZX21901 itself does not contribute to ppm error.
43. Driven by SRC output of main clock, 100.00 MHz PLL Mode or Bypass mode
44. Driven by CPU output of main clock, 133.33 MHz PLL Mode or Bypass mode
Table 17. POWER MANAGEMENT TABLE
Inputs
Control Bits/Pins
PWRGD/PWRDN# CLK_IN/CLK_IN# SMBus EN bit OE# Pin
DIF(5:12) /
DIF(5:12)#
Other DIF/
DIF#
0 X X X Hi−Z (Note 45) Hi−Z (Note 45)
0 X Hi−Z (Note 45) Hi−Z (Note 45)
1
1
0
Running
Running
Running
1 1 Hi−Z (Note 45) Running
45. Due to external pull down resistors, HI−Z results in Low/Low on the True/Complement outputs
Outputs
FB_OUT /
FB_OUT#
Hi−Z (Note 45)
Running
Running
Running
PLL
State
OFF
ON
ON
ON
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