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PDF NB3N51044 Data sheet ( Hoja de datos )
| Número de pieza | NB3N51044 | |
| Descripción | Quad HCSL / LVDS Clock Generator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB3N51044
3.3 V, Crystal to 100 MHz /
125 MHz Quad HCSL / LVDS
Clock Generator
The NB3N51044 is a precision, low phase noise clock generator that
supports PCI Express and sRIO clock requirements. The device
accepts a 25 MHz fundamental mode parallel resonant crystal or a
25 MHz single ended reference clock signal and generates four
differential HCSL/LVDS outputs (See Figure 10 for LVDS interface)
of 100 MHz or 125 MHz clock frequency based on frequency select
input F_SEL. NB3N51044 is configurable to bypass the PLL from
signal path using BYPASS, and provides the output frequency through
the divider network. All clock outputs can be individually enabled /
disabled through hardware input pins OE[3:0]. In addition, device can
be reset using Master Reset input pin MR_OE#.
Features
• Uses 25 MHz Fundamental Crystal or Reference Clock Input
• Four Low Skew HCSL or LVDS Outputs
• Output Frequency Selection of 100 MHz or 125 MHz
• Individual OE Tri−States Outputs
• Master Reset and BYPASS Modes
• PCIe Gen 1, Gen 2, Gen 3 Compliant
• Typical Phase Jitter @ 125 MHz (Integrated 1.875 MHz to 20 MHz):
0.2 ps
• Typical Cycle−Cycle Jitter @ 100 MHz (10k cycles): 20 ps
• Phase Noise @ 100 MHz:
Offset Noise Power
100 Hz −101 dBc/Hz
1 kHz −123 dBc/Hz
10 kHz −133 dBc/Hz
100 kHz −136 dBc/Hz
1 MHz −141 dBc/Hz
10 MHz −155 dBc/Hz
• Operating Supply Voltage Range 3.3 V ±5%
• Industrial Temperature Range −40°C to +85°C
• Functionally Compatible with ICS841604I with enhanced performance
• These are Pb−Free Devices
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MARKING DIAGRAM
TSSOP−28
DT SUFFIX
CASE 948AA
NB3N5
1044G
ALYW
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Applications
• Networking
• Consumer
• Computing and Peripherals
• Industrial Equipment
• PCIe Clock Generation Gen 1, Gen 2 and Gen 3
End Products
• Switch and Router
• Set Top Box, LCD TV
• Servers, Desktop Computers
• Automated Test Equipment
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 1
1
Publication Order Number:
NB3N51044/D
1 page  
NB3N51044
Table 8. DC ELECTRICAL CHARACTERISTICS (VDD = 3.3 V ± 5%, GND = 0 V, TA = −40°C to 85°C, Note 4)
Symbol
Parameter
Min Typ Max Unit
VDD Power Supply Voltage
3.135
IDD Power Supply Current when all outputs are ON, OE[3:0] = 1, FCLKOUT = 125 MHz
IOFF Power Supply Current when all outputs are set OFF, OE[3:0] = 0
VIH Input HIGH Voltage (XIN, REF_IN, REF_SEL, BYPASS, F_SEL, MR_OE#)
2.0
VIL Input LOW Voltage (XIN, REF_IN, REF_SEL, BYPASS, F_SEL, MR_OE#)
GND−0.3
IIH Input Leackage on logic High current at all input pins
IIL Input Leackage on logic Low current at all input pins
−5
VOH Output HIGH Voltage for HCSL output (Note 5)
660
VOL Output LOW Voltage for HCSL output (Note 5)
−150
VMAX Absolute Maximum Voltage, Measured Single ended including overshoot (Notes 5, 6)
VMIN Absolute Minimum Voltage, Measured Single ended including undershoot (Notes 5, 7) −300
VCROSS Crossing Voltage Magnitude (Absolute) for HCSL output (Notes 5, 8, 9)
250
DVCROSS Change in Magnitude of Vcross for HCSL Output (Notes 5, 8, 10)
VRB Ring Back Voltage measured differentially (Note 11)
−100
3.3
45
3.465
126
50
VDD+0.3
0.8
150
850
1150
550
150
100
V
mA
mA
V
V
mA
mA
mV
mV
mV
mV
mV
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurement taken with outputs terminated with RS = 33.2 W, RL = 49.9 W, with test load capacitance of 2 pF and current biasing resistor
set at RREF = 475 W. See Figure 9. Guaranteed by characterization.
5. Measurement taken from single-ended waveform
6. Defined as the maximum instantaneous voltage value including positive overshoot
7. Defined as the maximum instantaneous voltage value including negative overshoot
8. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx-.
9. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
10. Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx-. This is maximum allowed variance in the VCROSS for
any particular system.
11. Differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before it is allowed to drop back into the
VRB ±100 differential range.
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5
5 Page 
NB3N51044
The outputs can be terminated to drive HCSL receiver
(see Figure 9) or LVDS receiver (see Figure 10). HCSL
output interface requires 49.9 W termination resistors to
GND for generating the output levels. LVDS output
HCSL INTERFACE
CLK0
CLK0
RL* = 33.2 W
RL* = 33.2 W
Zo = 50 W
Zo = 50 W
NB3N51044
IREF
CLK1
CLK1
RL* = 33.2 W
RL* = 33.2 W
*Optional
RREF = 475 W
Zo = 50 W
Zo = 50 W
interface may not require the 100 W near the LVDS receiver
if the receiver has internal 100 W termination. An optional
series resistor RL may be connected to reduce the overshoots
in case of impedance mismatch.
RL = 49.9 W
RL = 49.9 W
HCSL
Receiver
RL = 49.9 W
RL = 49.9 W
Figure 9. Typical Termination for HCSL Output Driver and Device Evaluation
LVDS COMPATIBLE INTERFACE
CLK0
CLK0
RL* = 33.2 W
RL* = 33.2 W
Zo = 50 W
Zo = 50 W
NB3N51044
100 W
RL = 150 W
100 W**
RL = 150 W
CLK1
CLK1
RL* = 33.2 W
RL* = 33.2 W
Zo = 50 W
Zo = 50 W
IREF
RREF = 475 W
*Optional
**Not required if LVDS receiver
has 100 W internal termination
100 W
RL = 150 W
100 W**
RL = 150 W
Figure 10. Typical Termination for LVDS Device Load
LVDS
Receiver
LVDS Device Load
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11
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| PDF Descargar | [ Datasheet NB3N51044.PDF ] | |
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