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PDF SH66L06A Data sheet ( Hoja de datos )
| Número de pieza | SH66L06A | |
| Descripción | 1K 4-bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH66L06A
1K 4-bit Micro-controller with LCD Driver
Features
SH6610C-based single-chip 4-bit micro-controller with
LCD driver
ROM: 1024 X 16 bits
RAM: 288 X 4 bits
- 32 System Control Register
- 256 Data memory
- 18 LCD RAM
Operation Voltage: 1.2V - 1.7V
8 CMOS Bi-directional I/O pads
4-Level Stack (Including Interrupts)
Two 8-bit Auto Re-Loaded Timers/Counters
Warm-Up Timer
Powerful Interrupt Sources:
- External interrupt (Low active)
- Timer0 interrupt
- Timer1 interrupt
- PORTB interrupt (Low active)
Oscillator (Code Option)
- Crystal Oscillator: 32.768kHz
- RC Oscillator:
131kHz
Instruction Cycle Time (4/fOSC)
LCD Driver:
- 18SEG X 4COM (1/4 Duty, 1/3 Bias)
- 18SEG X 3COM (1/3 Duty, 1/2 Bias)
Two Low Power Operation Modes: HALT And STOP
Built-in Watchdog Timer (Code Option)
Built-in Voltage Doubler And Tripler Charge Pump
Circuit
Built-in Alarm Generator
Low power consumption
Bonding option for multi-code software
Available in CHIP FORM
General Description
SH66L06A is a single-chip 4-bit micro-controller. This device integrates a SH6610C CPU core, SRAM, timer, alarm generator,
LCD driver, I/O port, voltage pump and program ROM. The SH66L06A is suitable for calculator application.
Pad Configuration
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PORTA0
PORTA1
PORTA2
PORTA3
PORTB0
PORTB1
1 56 55 54 53 52 51 50 49 48 47 46 45 44
2 43
3 42
4 41
5 40
6 39
7
8
SH66L06A
38
37
9 36
10 35
11 34
12 33
13 32
14 31
15
19 22
30
16 17 18 B0 20 21 B1 23 24 25 26 27 28 29
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM4
COM3
COM2
COM1
1 V2.0
1 page  
SH66L06A
2.2. Configuration of System Register:
Address
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A - $0C
$0D
$0E
$0F
$10
$11
$12
Bit 3
IEX
IRQX
-
-
T0L.3
T0H.3
T1L.3
T1H.3
PA.3
PB.3
-
-
TBR.3
INX.3
DPL.3
-
-
$13 -
$14 AEC3
$15 PPULL
$16 - $19
$1A
$1B
$1C
$1D - $1F
-
WDT
PACR.3
PBCR.3
-
Bit 2
IET0
IRQT0
T0M.2
T1M.2
T0L.2
T0H.2
T1L.2
T1H.2
PA.2
PB.2
-
-
TBR.2
INX.2
DPL.2
DPM.2
DPH.2
LCDOFF
AEC2
1
-
-
PACR.2
PBCR.2
-
Bit 1
IET1
IRQT1
T0M.1
T1M.1
T0L.1
T0H.1
T1L.1
T1H.1
PA.1
PB.1
-
B1
TBR.1
INX.1
DPL.1
DPM.1
DPH.1
HLM
AEC1
1
-
-
PACR.1
PBCR.1
-
Bit 0
IEP
IRQP
T0M.0
T1M.0
T0L.0
T0H.0
T1L.0
T1H.0
PA.0
PB.0
-
B0
TBR.0
INX.0
DPL.0
DPM.0
DPH.0
PAM
AEC0
-
-
-
PACR.0
PBCR.0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
-
Remarks
Interrupt enable flags register
Interrupt request flags register
Bit2-0: Timer0 Mode register
Bit2-0: Timer1 Mode register
Timer0 load/counter register low nibble register
Timer0 load/counter register high nibble register
Timer1 load/counter register low nibble register
Timer1 load/counter register high nibble register
PORTA data register
PORTB data register
Reserved
Bit1-0: Bonding option
Table Branch register
Pseudo index register
Data pointer for INX low nibble register
Data pointer for INX middle nibble register
Data pointer for INX high nibble register
Bit0: PORTA.1, PORTA.2 as Alarm O/P control register
Bit1: Heavy load Mode control register
Bit2: LCD display OFF control register
Alarm Envelope Control register
Bit2-1: must keep it to “1”. In the User’s program.
Bit3: Port pull-up control register
Reserved
Watchdog timer overflow flag register
PORTA input/output control register
PORTB input/output control register
Reserved
For SH66L06A, after the chip reset, please first write *11*B to $15. Otherwise, the halt current and stop current will be abnormal
3. ROM
The ROM can address 1024 X 16 bits of program area from $000 to $3FF.
3.1. Vector Address Area ($000 to $004)
The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt
service routine such as starting vector address.
Address
$000
Instruction
JMP*
Remarks
Jump to RESET service routine
$001
JMP*
Jump to External interrupt service routine
$002
JMP*
Jump to TIMER0 service routine
$003
JMP*
Jump to TIMER1 service routine
$004
JMP*
Jump to PB service routine (PORTB)
* JMP instruction can be replaced by any instruction.
5
5 Page 
SH66L06A
8. Interrupt
Four interrupt sources are available on SH66L06A:
- External interrupt (Low active)
- Timer0 interrupt
- Timer1 interrupt
- PORTB interrupt (Low active)
Interrupt Control Bits and Interrupt Service
The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the program.
Those flags are clear to “0” at initialization by the chip reset.
System Register:
Address
$00
$01
Bit 3
IEX
IRQX
Bit 2
IET0
IRQT0
Bit 1
IET1
IRQT1
Bit 0
IEP
IRQP
R/W
R/W
R/W
Remarks
Interrupt enable flags register
Interrupt request flags register
When IEx is set to “1” and the interrupt request is generated (IRQx is 1), the interrupt will be activated and vector address will be
generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be
saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx)
are cleared to “0” automatically, so when IRQx is 1 and IEx is set to “1” again, the interrupt will be activated and vector address
will be generated from the priority PLA corresponding to the interrupt sources.
12345
Inst.cycle
Instruction
Execution
N
Instruction
Execution
I1
Instruction
Execution
I2
Interrupt Generated
Interrupt Accepted
Vector Generated
Stacking
Fetch Vector address
Reset IE.X
Start at vector address
Interrupt Servicing Sequence Diagram
Interrupt Nesting
During the CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt. The servicing
sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is ready and the
instruction of execution N is IE enabled, then the interrupt will start immediately after the next two instruction executions.
However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will be
terminated.
External Interrupt
When Bit3 of system register $00 (IEX) is set to “1”, the external interrupt will be enabled, and a low level applying on the
external interrupt I/O port will generate an external interrupt. External Interrupt can be used to wake the CPU from HALT or
STOP mode.
Timer Interrupt
The input clocks of Timer0 and Timer1 are based on system clock source. The timer overflow from $FF to $00 will generate an
internal interrupt request (IRQT0 or IRQT1 = 1), If the interrupt enable flag is enabled (IET0 or IET1 = 1), a timer interrupt
service routine will start. Timer interrupt can also be used to wake the CPU from HALT mode.
Port Low Active Interrupt
Only the digital input port can generate a port interrupt. The analog input cannot generate an interrupt request.
Any one of the I/O input port applying with a low level would generate an interrupt request (IRQP = 1). In order to avoid
multi-responses, it is strongly recommended that the relative input port cannot be connected with a low level all the time. Port
Interrupt can be used to wake the CPU from HALT or STOP mode.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH66L06A.PDF ] | |
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