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PDF SX1231JIMLTRT Data sheet ( Hoja de datos )

Número de pieza SX1231JIMLTRT
Descripción Low Power Integrated UHF Transceiver
Fabricantes Semtech Corporation 
Logotipo Semtech Corporation Logotipo



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SX1231J
WIRELESS & SENSING
SX1231J Transceiver
Low Power Integrated UHF Transceiver
DATASHEET
RFIO
VBAT1&2
VR_ANA
VR_DIG
Power Distribution System
LNA
Σ/Δ
Single to
Mixers
Modulators
Differential
RC
Oscillator
GND
VR_PA
PA_BOOST
PA0
Ramp &
Control
PA1&2
Tank
Inductor
Loop
Filter
Division by
2, 4 or 6
Frac-N PLL
Synthesizer
XO
32 MHz
XTAL
RSSI
AFC
GND
RESET
SPI
RXTX
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
GENERAL DESCRIPTION
The SX1231J is an ARIB compliant highly integrated RF
transceiver which operates over all Japanese sub-GHz
frequency bands. Its highly integrated digital architecture
minimizes external components and provides flexibility for
optimizing the system parameters and performance. The
high sensitivity and exceptional blocking performance
combined with optimized IIP3 maximizes the range in
harshest environments. The industries lowest sleep current,
fastest wake times, and low receive current extend the
battery life for any application. The transmit output power is
programmable up to +17dBm and delivers constant
performance over the battery voltage lifetime. TrueRF™
technology enables a low-cost external component count
(eliminating SAW filter) while still satisfying ARIB, FCC, and
ETSI regulations. The device supports IEEE 15.4d/g
mandatory modes.
APPLICATIONS
Š Smart metering and IEEE15.4d/g
Š Wireless sensor networks
Š Home and building automation
Š Wireless alarm and security systems
Š Industrial monitoring and control
Š Active RFID tags
Š Remote keyless entry (RKE) and automotive
KEY PRODUCT FEATURES
Š High Sensitivity: down to -120 dBm at 1.2 kbps
Š Robust Selectivity: 42dB at 25kHz offset
Š Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,
80 dB Blocking Immunity, no Image Frequency response
Š Low current receive mode = 16 mA
Š Low current sleep mode with register retention =100nA
Š Programmable TX Power: -18 to +17 dBm in 1dB steps
Š Constant RF performance over VDD voltage range
Š FSK bit rates up to 300 kb/s
Š Fully integrated synthesizer with a resolution of 61 Hz
Š FSK, GFSK, MSK, GMSK and OOK modulations
Š Built-in bit synchronizer for clock recovery
Š Incoming sync word recognition
Š 115 dB+ dynamic range RSSI
Š Automatic RF sense with ultra-fast AFC
Š Packet engine with CRC, AES-128, and 66-byte FIFO
Š Built-in temperature sensor and low battery indicator
ORDERING INFORMATION
Part Number Package Delivery MOQ / Multiple
MARKETS
Š Japan: ARIB STD-T67 from 426 to 470 MHz
Š Japan: ARIB STD-T108 from 915 to 930 MHz
SX1231JIMLTRT QFN24
Tape &
Reel
3000 pieces
Š Pb-free, Halogen free, RoHS/WEEE compliant product
Rev 2 - April 2012
Page 1
www.semtech.com

1 page




SX1231JIMLTRT pdf
SX1231J
WIRELESS & SENSING
DATASHEET
This product datasheet contains a detailed description of the SX1231J performance and functionality. Please consult the
Semtech website www.semtech.com for the latest updates or errata.
1. General Description
The SX1231J is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The
SX1231J's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high
level of integration reduces the external BOM to a handful of passive decoupling and matching components. It is intended
for use as high-performance, low-cost FSK and OOK RF transceiver for robust frequency agile, half-duplex bi-directional
RF links, and where stable and constant RF performance is required over the full operating range of the device down to
1.8V.
Coupled with a link budget in excess of 135 dB, the advanced system features of the SX1231J include a 66 byte TX/RX
FIFO, configurable automatic packet handler, listen mode, temperature sensor and configurable DIOs which greatly
enhance system flexibility whilst at the same time significantly reducing MCU requirements.
The SX1231J complies with Japanese ARIB regulatory requirements and is available in a 5x 5 mm QFN 24 lead package.
1.1. Simplified Block Diagram
VBAT1&2
VR_ANA
VR_DIG
Power Distribution System
RC
Oscillator
RFIO
LNA Σ/Δ
Single to
Mixers
Modulators
Differential
RESET
SPI
GND
VR_PA
PA_BOOST
PA0
Ramp &
Control
PA1&2
Tank
Inductor
Loop
Filter
Division by
2, 4 or 6
Frac-N PLL
Synthesizer
XO
32 MHz
RSSI
AFC
RXTX
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
Frequency Synthesis
Receiver Blocks
XTAL
GND
Transmitter Blocks
Control Blocks
Figure 1. Block Diagram
Primarily Analog
Primarily Digital
Rev 2 - April 2012
Page 5
www.semtech.com

5 Page





SX1231JIMLTRT arduino
WIRELESS & SENSING
SX1231J
DATASHEET
IMR_OOK
Image rejection in OOK mode
Wanted signal level = -106 dBm
27 30
- dB
TS_RE
Receiver wake-up time, from PLL RxBw = 10 kHz, BR = 4.8 kb/s
locked state to RxReady
RxBw = 200 kHz, BR = 100 kb/s
- 1.7 - ms
- 96 - us
TS_RE_AGC Receiver wake-up time, from PLL RxBw= 10 kHz, BR = 4.8 kb/s
locked state, AGC enabled
RxBw = 200 kHz, BR = 100 kb/s
- 3.0
163
ms
us
TS_RE_AGC Receiver wake-up time, from PLL RxBw= 10 kHz, BR = 4.8 kb/s
&AFC
lock state, AGC and AFC enabled RxBw = 200 kHz, BR = 100 kb/s
4.8 ms
265 us
TS_FEI
FEI sampling time
Receiver is ready
- 4.Tbit - -
TS_AFC
AFC Response Time
Receiver is ready
- 4.Tbit - -
TS_RSSI
RSSI Response Time
Receiver is ready
- 2.Tbit - -
DR_RSSI
RSSI Dynamic Range
AGC enabled
Min - -115 - dBm
Max - 0 - dBm
* Set SensitivityBoost in RegTestLna to 0x2D to reduce the noise floor in the receiver
2.4.4. Transmitter
Table 7 Transmitter Specification
Symbol Description
Conditions
Min Typ Max Unit
RF_OP
RF output power in 50 ohms
On RFIO pin
Programmable with 1dB steps Max - +13 - dBm
Min - -18 - dBm
RF_OPH
ΔRF_OP
Max RF output power, on
PA_BOOST pin
RF output power stability
With external match to 50 ohms
From VDD=1.8V to 3.6V
- +17 - dBm
- +/-0.3 - dB
PHN
Transmitter Phase Noise
50 kHz Offset from carrier
868 / 915 MHz bands
-
-95
- dBc/
434 / 315 MHz bands
-
-99
- Hz
ACP
Transmitter adjacent channel
power (measured at 25 kHz off-
set)
BT=0.5 . Measurement conditions as
defined by EN 300 220-1 V2.1.1
-
- -37 dBm
TS_TR
Transmitter wake up time, to the Frequency Synthesizer enabled,
first rising edge of DCLK
PaRamp = 10 us, BR = 4.8 kb/s.
- 120 - us
Rev 2 - April 2012
Page 11
www.semtech.com

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