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W83195CG-413 Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83195CG-413
Beschreibung Clock Generator
Hersteller Winbond
Logo Winbond Logo 




Gesamt 27 Seiten
W83195CG-413 Datasheet, Funktion
Winbond Clock Generator
W83195WG-413
W83195CG-413
For ATI P4 Chipset
Date: Feb/27/2006 Revision: 0.6






W83195CG-413 Datasheet, Funktion
W83195WG-413/W83195CG-413
STEPLESS FOR ATI P4 CLOCK GENERATOR
3. PIN CONFIGURATION
XIN
XOUT
VDD48
USB_48
GND
VTT_PG#/PD
SCLK
SDATA
&FSC
&CLKREQA#
&CLKREQB#
SRCT7
SRCC7
VDDSRC
GND
SRCT6
SRCC6
SRCT5
SRCC5
GND
VDDSRC
SRCT4
SRCC4
SRCT3
SRCC3
GND
ATIGT1
ATIGC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
#: Active low
*: Internal pull up resistor 120K to VDD
&: Internal Pull-down resistor 120K to GND
56 VDDREF
55 GND
54 &FSA/REF0
53 &FSB/REF1
52 REF2
51 VDDPCI
50 &CK410#/PCICLK0
49 GND
48 *CPU_STOP#
47 CPUT0
46 CPUC0
45 VDDCPU
44 GND
43 CPUT1
42 CPUC1
41 CPUT2_ITP
40 CPUC2_ITP
39 VDDA
38 GNDA
37 IREF
36 GND
35 VDDSRC
34 SRCT0
33 SRCC0
32 VDDATI
31 GND
30 ATIGT0
29 ATIGC0
4. BLOCK DIAGRAM
XIN
XOUT
FS(A:C)
C R # _ (A :B )
VTT_PG#
CK410#
CPU_STOP#
PD
SDATA
SCLK
A T IG L O O P
USBLOOP
CPULOOP
Spread
Spectrum
XTAL
OSC
Divider
Divider
& Sync
SRCLOOP
Spread
Spectrum
VCOCLK
M /N /R a tio
ROM
Divider
& Snyc
Latch
&POR
C o n tro l
Logic
& C o n fig
Register
I2C
Interface
2
ATIGT 0:1
ATIGC 0:1
2
48MHz
3
REF 0:2
3
CPUT 0:2
CPUC 0:2
3
6
SRCT 0,3:7
SRCC 0,3:7
6
PCI0
475
Publication Release Date: Feb 2006
- 2 - Revision 0.6

6 Page









W83195CG-413 pdf, datenblatt
5 CLREQB5#_Ctr
4 CLREQB4#_Ctr
3 CLREQB3#_Ctr
2 CLREQB0#_Ctr
1 PCIEN
0 Reserved
W83195WG-413/W83195CG-413
STEPLESS FOR ATI P4 CLOCK GENERATOR
SRCCLK5 is controlled by the CLREQB# pin
0 1: Controllable
0: Uncontrollable
SRCCLK4 is controlled by the CLREQB# pin
0 1: Controllable
0: Uncontrollable
SRCCLK3 is controlled by the CLREQB# pin
0 1: Controllable
0: Uncontrollable
SRCCLK0 is controlled by the CLREQB# pin
0 1: Controllable
0: Uncontrollable
PCI0 output control
1 1: Enable
0: Disable
R/W
R/W
R/W
R/W
R/W
1 Reserved
R/W
7.5 Register 4: ( Default : FEh)
BIT
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
7 CPU2S_EN
6 CPU1S_EN
5 CPU0S_EN
4 REFEN<2>
3 REFEN<1>
2 REFEN<0>
1 F48EN
CPU_STOP# pin control.
1 1: Enable CPUCLK2 stop feature
0: Disable stop feature
CPU_STOP# pin control.
1 1: Enable CPUCLK1 stop feature
0: Disable stop feature
CPU_STOP# pin control.
1 1: Enable CPUCLK0 stop feature
0: Disable stop feature
PREF2 output control
1 1: Enable
0: Disable
PREF1 output control
1 1: Enable
0: Disable
PREF0 output control
1 1: Enable
0: Disable
1 PUSB48 output control
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Publication Release Date: Feb 2006
- 8 - Revision 0.6

12 Page





SeitenGesamt 27 Seiten
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