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74HCT30D Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 74HCT30D
Beschreibung 8-input NAND gate
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 16 Seiten
74HCT30D Datasheet, Funktion
74HC30; 74HCT30
8-input NAND gate
Rev. 6 — 27 December 2012
Product data sheet
1. General description
The 74HC30; 74HCT30 is an 8-input NAND gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For 74HC30: CMOS level
For 74HCT30: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74HC30N
40 C to +125 C DIP14
74HCT30N
74HC30D
40 C to +125 C SO14
74HCT30D
74HC30DB
40 C to +125 C SSOP14
74HCT30DB
74HC30PW
40 C to +125 C TSSOP14
74HCT30PW
Description
plastic dual in-line package; 14 leads (300 mil)
Version
SOT27-1
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT337-1
SOT402-1






74HCT30D Datasheet, Funktion
NXP Semiconductors
74HC30; 74HCT30
8-input NAND gate
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
CI input
capacitance
- 3.5 -
-
-
-
- pF
74HCT30
VIH HIGH-level VCC = 4.5 V to 5.5 V
input voltage
2.0 1.6 -
2.0
-
2.0
-V
VIL LOW-level VCC = 4.5 V to 5.5 V
input voltage
- 1.2 0.8
-
0.8
-
0.8 V
VOH
VOL
II
ICC
ICC
CI
HIGH-level
output voltage
LOW-level
output voltage
input leakage
current
supply current
additional
supply current
input
capacitance
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
IO = 4.0 mA
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
IO = 4.0 mA
VI = VCC or GND;
VCC = 5.5 V
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
per input pin;
VI = VCC 2.4 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
4.4
3.98
-
-
-
-
-
-
4.5
4.32
0
0.15
-
-
60
3.5
-
-
0.1
0.26
0.1
2.0
216
-
4.4
3.84
-
-
-
-
-
-
-
-
0.1
0.33
1
20
275
-
4.4
3.7
-
-
-
-
-
-
-V
-V
0.1 V
0.4 V
1 A
40 A
294 A
- pF
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit see Figure 6.
Symbol Parameter
Conditions
74HC30
tpd propagation delay A, B, C, D, E, F, G, H to Y;
see Figure 5
VCC = 2.0 V
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
tt
transition time
see Figure 5
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
25 C
40 C to +125 C Unit
Min Typ Max Max
Max
(85 C) (125 C)
[1]
-
-
-
-
[2]
-
-
-
41 130 165
15 26
33
12 -
-
12 22
28
19 75
7 15
6 13
95
19
16
195 ns
39 ns
- ns
33 ns
110 ns
22 ns
19 ns
74HC_HCT30
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 27 December 2012
© NXP B.V. 2012. All rights reserved.
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6 Page









74HCT30D pdf, datenblatt
NXP Semiconductors
74HC30; 74HCT30
8-input NAND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
y
Z
14
8
c
EA
X
HE v M A
pin 1 index
1
e
7
bp
wM
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
D (1) E (2)
e
5.1
4.9
4.5
4.3
0.65
HE
6.6
6.2
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT402-1
MO-153
L Lp Q v w y Z (1) θ
1
0.75 0.4
0.50 0.3
0.2 0.13
0.1
0.72
0.38
8o
0o
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 10. Package outline SOT402-1 (TSSOP14)
74HC_HCT30
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 27 December 2012
© NXP B.V. 2012. All rights reserved.
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