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74HCT27PW Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 74HCT27PW
Beschreibung Triple 3-input NOR gate
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 17 Seiten
74HCT27PW Datasheet, Funktion
74HC27; 74HCT27
Triple 3-input NOR gate
Rev. 4 — 5 June 2013
Product data sheet
1. General description
The 74HC27; 74HCT27 is a triple 3-input NOR gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC27: CMOS level
For 74HCT27: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
Version
74HC27N
40 C to +125 C DIP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
74HCT27N
74HC27D
40 C to +125 C SO14
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HCT27D
74HC27DB 40 C to +125 C SSOP14
74HCT27DB
plastic shrink small outline package; 14 leads; body width SOT337-1
5.3 mm
74HC27PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body
74HCT27PW
width 4.4 mm
SOT402-1
74HC27BQ 40 C to +125 C
74HCT27BQ
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
SOT762-1






74HCT27PW Datasheet, Funktion
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
10. Dynamic characteristics
Table 7. Dynamic characteristics type 74HC27; 74HCT27
GND = 0 V; for load circuit see Figure 7.
Symbol Parameter
Conditions
Min
74HC27
tpd propagation delay nA, nB, nC to nY; see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
tt
transition time
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
CPD power dissipation per package; VI = GND to VCC
capacitance
74HCT27
tpd propagation delay nA, nB, nC to nY; see Figure 6
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
tt
transition time
VCC = 4.5 V; see Figure 6
CPD power dissipation per package;
capacitance
VI = GND to VCC 1.5 V
[1]
[2]
[3]
[1]
[2]
[3]
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
-
-
-
-
-
-
-
-
-
-
-
-
25 C
Typ
28
10
8
8
19
7
6
24
12
10
7
30
40 C to +125 C Unit
Max Max
Max
(85 C) (125 C)
90 115 135 ns
18 23
27 ns
--
- ns
15 20
23 ns
75 95 110 ns
15 19
22 ns
13 16
19 ns
--
- pF
21 26
--
15 19
--
32 ns
- ns
22 ns
- pF
74HC_HCT27
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
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6 Page









74HCT27PW pdf, datenblatt
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
y
Z
14
8
c
EA
X
HE v M A
pin 1 index
1
e
7
bp
wM
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
D (1) E (2)
e
5.1
4.9
4.5
4.3
0.65
HE
6.6
6.2
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT402-1
MO-153
L Lp Q v w y Z (1) θ
1
0.75 0.4
0.50 0.3
0.2 0.13
0.1
0.72
0.38
8o
0o
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 11. Package outline SOT402-1 (TSSOP14)
74HC_HCT27
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
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