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ADSP-21487 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-21487
Beschreibung SHARC Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-21487 Datasheet, Funktion
SHARC Processor
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip
ROM
Up to 450 MHz operating frequency
Code compatible with all other members of the SHARC family
The ADSP-2148x processors are available with unique audio-
centric peripherals, such as the digital applications
interface, serial ports, precision clock generators, S/PDIF
transceiver, asynchronous sample rate converters, input
data port, and more
For complete ordering information, see Ordering Guide on
Page 66
Qualified for automotive applications
SIMD Core
Instruction
Cache
5 Stage
Sequencer
DAG1/2
Core
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG THERMAL
DIODE
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
DMD
64-BIT
S
DMD
64-BIT
Core Bus
PMD
64-BIT
Cross Bar
PMD 64-BIT
EPD BUS 64-BIT
PERIPHERAL BUS
32-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
IOD1
32-BIT
PERIPHERAL BUS
CORE
FLAGS/
PWM3-1
PCG
C-D
TIMER
1-0
TWI
SPI/B UART
IOD0 BUS
S/PDIF PCG
Tx/Rx A-D
ASRC PDAP/ SPORT
3-0 IDP 7-0
7-0
FFT
FIR
IIR
DTCP/
MTM
SPEP BUS
CORE PWM
WDT FLAGS 3-0
EP
AMI
SDRAM
CTL
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
Figure 1. Functional Block Diagram
External Port Pin MUX
Peripherals
External
Port
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADSP-21487 Datasheet, Funktion
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory, all in a single
instruction.
Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions from
previous SHARC processors, the ADSP-2148x supports new
instructions of 16 and 32 bits. This feature, called Variable
Instruction Set Architecture (VISA), drops redundant/unused
bits within the 48-bit instruction to create more efficient and
compact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
SDRAM memory. This support is not extended to the
asynchronous memory interface (AMI). Source modules need
to be built using the VISA option, in order to allow code genera-
tion tools to create these more efficient opcodes.
On-Chip Memory
The ADSP-21483 and the ADSP-21488 processors contain
3 Mbits of internal RAM (Table 3) and the ADSP-21486,
ADSP-21487, and ADSP-21489 processors contain 5 Mbits of
internal RAM (Table 4). Each memory block supports single-
cycle, independent accesses by the core processor and I/O
processor.
Table 3. Internal Memory Space (3 MBits—ADSP-21483/ADSP-21488)1
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 Bits)
Extended Precision Normal or
Instruction Word (48 Bits)
Normal Word (32 Bits)
Short Word (16 Bits)
Block 0 ROM (Reserved)
0x0004 0000–0x0004 7FFF
Block 0 ROM (Reserved)
0x0008 0000–0x0008 AAA9
Block 0 ROM (Reserved)
0x0008 0000–0x0008 FFFF
Block 0 ROM (Reserved)
0x0010 0000–0x0011 FFFF
Reserved
0x0004 8000–0x0004 8FFF
Reserved
0x0008 AAAA–0x0008 BFFF
Reserved
0x0009 0000–0x0009 1FFF
Reserved
0x0012 0000–0x0012 3FFF
Block 0 SRAM
0x0004 9000–0x0004 CFFF
Block 0 SRAM
0x0008 C000–0x0009 1554
Block 0 SRAM
0x0009 2000–0x0009 9FFF
Block 0 SRAM
0x0012 4000–0x0013 3FFF
Reserved
0x0004 D000–0x0004 FFFF
Reserved
0x0009 1555–0x0009 FFFF
Reserved
0x0009 A000–0x0009 FFFF
Reserved
0x0013 4000–0x0013 FFFF
Block 1 ROM (Reserved)
0x0005 0000–0x0005 7FFF
Block 1 ROM (Reserved)
0x000A 0000–0x000A AAA9
Block 1 ROM (Reserved)
0x000A 0000–0x000A FFFF
Block 1 ROM (Reserved)
0x0014 0000–0x0015 FFFF
Reserved
0x0005 8000–0x0005 8FFF
Reserved
0x000A AAAA–0x000A BFFF
Reserved
0x000B 0000–0x000B 1FFF
Reserved
0x0016 0000–0x0016 3FFF
Block 1 SRAM
0x0005 9000–0x0005 CFFF
Block 1 SRAM
0x000A C000–0x000B 1554
Block 1 SRAM
0x000B 2000–0x000B 9FFF
Block 1 SRAM
0x0016 4000–0x0017 3FFF
Reserved
0x0005 D000–0x0005 FFFF
Reserved
0x000B 1555–0x000B FFFF
Reserved
0x000B A000–0x000B FFFF
Reserved
0x0017 4000–0x0017 FFFF
Block 2 SRAM
0x0006 0000–0x0006 1FFF
Block 2 SRAM
0x000C 0000–0x000C 2AA9
Block 2 SRAM
0x000C 0000–0x000C 3FFF
Block 2 SRAM
0x0018 0000–0x0018 7FFF
Reserved
0x0006 2000– 0x0006 FFFF
Reserved
0x000C 2AAA–0x000D FFFF
Reserved
0x000C 4000–0x000D FFFF
Reserved
0x0018 8000–0x001B FFFF
Block 3 SRAM
0x0007 0000–0x0007 1FFF
Block 3 SRAM
0x000E 0000–0x000E 2AA9
Block 3 SRAM
0x000E 0000–0x000E 3FFF
Block 3 SRAM
0x001C 0000–0x001C 7FFF
Reserved
0x0007 2000–0x0007 FFFF
Reserved
0x000E 2AAA–0x000F FFFF
Reserved
0x000E 4000–0x000F FFFF
Reserved
0x001C 8000–0x001F FFFF
1 Some ADSP-2148x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog
Devices sales representative for additional details.
The processor’s SRAM can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data, 106.7k
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to 5 megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
floating-point storage format is supported that effectively dou-
bles the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each mem-
ory block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
The memory maps in Table 3 and Table 4 display the internal
memory address space of the processors. The 48-bit space sec-
tion describes what this address range looks like to an
Rev. C | Page 6 of 68 | June 2015

6 Page









ADSP-21487 pdf, datenblatt
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Details on power consumption and Static and Dynamic current
consumption can be found at Total Power Dissipation on
Page 20. Also see Operating Conditions on Page 18 for more
information.
The following are SVS features.
• SVS is applicable only to 450 MHz models (not applicable
to 400 MHz or lower frequency models).
• Each individual SVS device includes a register (SVS_DAT)
containing the unique SVS voltage set at the factory, known
as SVSNOM.
• The SVSNOM value is the intended set voltage for the
VDD_INT voltage regulator.
• No dedicated pins are required for SVS. The TWI serial bus
is used to communicate SVSNOM to the voltage regulator.
• Analog Devices recommends a specific voltage regulator
design and initialization code sequence that optimizes the
power-up sequence.
The Engineer-to-Engineer Note “Static Voltage Scaling for
ADSP-2148x Processors” (EE-357) contains the details of
the regulator design and the initialization requirements.
• Any differences from the Analog Devices recommended
programmable regulator design must be reviewed by Ana-
log Devices to ensure that it meets the voltage accuracy and
range requirements.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-2148x pro-
cessors to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processor stacks. The processor’s JTAG interface ensures that
the emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate emulator hardware user’s guide.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embed-
ded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
EclipseTM framework. Supporting most Analog Devices proces-
sor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports proces-
sor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZ-
KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of Cross-
Core Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZ-
KITs or any custom system utilizing supported Analog Devices
processors.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly inte-
grate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware pack-
ages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Board Support Packages for Evaluation Hardware
Software support for the EZ-KIT Lite evaluation boards and EZ-
Extender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZ-
Extender product. The link is found in the Product Download
area of the product web page.
Rev. C | Page 12 of 68 | June 2015

12 Page





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