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PDF 74HC05-Q100 Data sheet ( Hoja de datos )
| Número de pieza | 74HC05-Q100 | |
| Descripción | Hex inverter | |
| Fabricantes | NXP Semiconductors | |
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74HC05-Q100
Hex inverter with open-drain outputs
Rev. 1 — 9 July 2012
Product data sheet
1. General description
The 74HC05-Q100 is a high-speed Si-gate CMOS device that complies with JEDEC
standard no. 7A.
The 74HC05-Q100 contains six inverters. The outputs of the 74HC05-Q100 are
open-drain and can be connected to other open-drain outputs to implement active-LOW
wired-OR or active-HIGH wired-AND functions. The open-drain outputs require pull-up
resistors to perform correctly.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide operating voltage 2.0 V to 6.0 V
Input levels:
For 74HC05-Q100: CMOS level
Latch-up performance exceeds 100 mA per JESD 78 Class II level A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
Multiple package options
1 page  
NXP Semiconductors
74HC05-Q100
Hex inverter with open-drain outputs
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
VIH HIGH-level VCC = 2.0 V
input voltage VCC = 4.5 V
1.5 1.2 -
3.15 2.4 -
1.5 -
3.15 -
1.5 -
3.15 -
V
V
VCC = 6.0 V
4.2 3.2 - 4.2 -
4.2 -
V
VIL LOW-level VCC = 2.0 V
input voltage VCC = 4.5 V
- 0.8 0.5 -
- 2.1 1.35 -
0.5 -
1.35 -
0.5 V
1.35 V
VCC = 6.0 V
- 2.8 1.8 -
1.8 -
1.8 V
VOL LOW-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V -
0 0.1 -
0.1 -
0.1 V
IO = 20 A; VCC = 4.5 V -
0 0.1 -
0.1 -
0.1 V
IO = 20 A; VCC = 6.0 V -
0 0.1 -
0.1 -
0.1 V
IO = 4.0 mA; VCC = 4.5 V -
0.15 0.26 -
0.33 -
0.4 V
IO = 5.2 mA; VCC = 6.0 V -
0.16 0.26 -
0.33 -
0.4 V
II input leakage VI = VCC or GND;
current
VCC = 6.0 V
- - ±0.1 -
±1 -
±1 A
IOZ OFF-state per input pin; VI = VIL;
- - ±0.5 - ±5.0 -
output current VO = VCC or GND;
other inputs at VCC or GND;
VCC = 6.0 V; IO = 0 A
±10 A
ICC supply current VI = VCC or GND; IO = 0 A; - - 2.0 -
VCC = 6.0 V
20 -
40 A
CI input
capacitance
- 3.5 - - - - - pF
74HC05_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 July 2012
© NXP B.V. 2012. All rights reserved.
5 of 15
5 Page 
NXP Semiconductors
74HC05-Q100
Hex inverter with open-drain outputs
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
D BA
terminal 1
index area
A
A1
E
c
detail X
terminal 1
index area
L
e
2
1
Eh
14
e1
b
6
vM C AB
wM C
7
e
8
y1 C
C
y
13 9
Dh
0 2.5
5 mm
X
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c D(1) Dh E(1) Eh e e1 L
v
w
y y1
mm
1
0.05 0.30
0.00 0.18
0.2
3.1 1.65
2.9 1.35
2.6
2.4
1.15
0.85
0.5
2
0.5
0.3
0.1 0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
EUROPEAN
PROJECTION
SOT762-1
---
MO-241
---
ISSUE DATE
02-10-17
03-01-27
Fig 10. Package outline SOT762-1 (DHVQFN14)
74HC05_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 July 2012
© NXP B.V. 2012. All rights reserved.
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