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PDF MB9BF504R Data sheet ( Hoja de datos )
| Número de pieza | MB9BF504R | |
| Descripción | 32-bit Microcontroller | |
| Fabricantes | Fujitsu | |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS706-00010-0v01-E
32-bit ARM Cortex-M3TM based Microcontroller
FM3 MB9B500 Series
MB9BF500N/R,
MB9BF504N/R, F505N/R, F506N/R
DESCRIPTION
The MB9B500 Series are a highly integrated 32-bit microcontroller that target for high-performance and
cost-sensitive embedded control applications.
The MB9B500 Series are based on the ARM Cortex-M3 Processor and on-chip Flash memory and SRAM,
and peripheral functions, including Motor Control Timers, ADCs and Communication Interfaces (USB,
CAN, UART, SIO, I2C, LIN).
Note: ARM and Cortex-M3 are the trademarks of ARM Limited in the EU and other countries.
Copyright2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.11
1 page  
PRELIMINARY
MB9B500 Series
Dual Timer (Two 32/16bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
・ Free-running
・ Periodic (=Reload)
・ One-shot
Watch Counter
The Watch counter is used for wake up from power saving mode.
・ Interval timer: up to 64s(Max.)@ Sub Clock : 32.768kHz
External Interrupt Controller Unit
・ Up to 16 external vectors
・ Include one non-maskable interrupt(NMI)
Watch dog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
MB9B500 series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low speed CR oscillator. Therefore,”Hardware" watchdog is
active in any power saving mode except STOP.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
・ CCITT CRC16 Generator Polynomial: 0x1021
・ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 ext. osc, 2 CR osc, and PLL) that are dynamically selectable.
・ Main Clock
: 4 to 48MHz
・ Sub Clock
: 32.768kHz
・ High-speed CR Clock : 4MHz
・ Low-speed CR Clock : 100kHz
・ PLL Clock
[Resets]
Reset requests from INITX pins, Power on reset, Software reset, watchdog timers reset, low voltage
detector reset and clock supervisor reset.
Clock Super Visor (CSV)
Clocks generated by CR oscillators are used to supervise abnormality of the external clocks.
・ External OSC clock failure (clock stop) is detected, reset is asserted.
・ External OSC frequency anomaly is detected, interrupt or reset is asserted.
DS706-00010-0v01-E
5
5 Page 
PRELIMINARY
BGA-112P-M04
MB9B500 Series
<Notes>
・ The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
・ In MB9BF500, GPIO function can not be used for P46, P47, P80, and P81.
DS706-00010-0v01-E
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB9BF504R.PDF ] | |
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