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PDF LM3S9B92 Data sheet ( Hoja de datos )

Número de pieza LM3S9B92
Descripción Microcontroller
Fabricantes Luminary Micro　
Logotipo Luminary Micro Logotipo



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No Preview Available ! LM3S9B92 Hoja de datos, Descripción, Manual

PRELIMINARY
LM3S9B92 Microcontroller
DATA SHEET
DS-LM3S9B92-4997
Copyright © 2007-2009 Luminary Micro, Inc.

1 page




LM3S9B92 pdf
LM3S9B92 Microcontroller
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2
9.3
9.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 291
Functional Description ............................................................................................................. 291
Data Control ........................................................................................................................... 293
Interrupt Control ...................................................................................................................... 294
Mode Control .......................................................................................................................... 295
Commit Control ....................................................................................................................... 295
Pad Control ............................................................................................................................. 296
Identification ........................................................................................................................... 296
Initialization and Configuration ................................................................................................. 296
Register Map .......................................................................................................................... 297
Register Descriptions .............................................................................................................. 300
10 External Peripheral Interface (EPI) ................................................................................. 342
10.1 EPI Block Diagram .................................................................................................................. 343
10.2 Functional Description ............................................................................................................. 344
10.2.1 Non-blocking reads ................................................................................................................. 344
10.2.2 DMA Operation ....................................................................................................................... 345
10.3 Initialization and Configuration ................................................................................................. 345
10.3.1 SDRAM mode ......................................................................................................................... 347
10.3.2 Host Bus Mode ....................................................................................................................... 348
10.3.3 General-Purpose Mode ........................................................................................................... 350
10.4 Register Map .......................................................................................................................... 352
10.5 Register Descriptions .............................................................................................................. 353
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.4
11.5
General-Purpose Timers ................................................................................................. 388
Block Diagram ........................................................................................................................ 388
Functional Description ............................................................................................................. 389
GPTM Reset Conditions .......................................................................................................... 390
32-Bit Timer Operating Modes .................................................................................................. 390
16-Bit Timer Operating Modes .................................................................................................. 391
DMA Operation ....................................................................................................................... 396
Initialization and Configuration ................................................................................................. 396
32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 396
32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 397
16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 397
16-Bit Input Edge-Count Mode ................................................................................................. 398
16-Bit Input Edge Timing Mode ................................................................................................ 399
16-Bit PWM Mode ................................................................................................................... 399
Register Map .......................................................................................................................... 400
Register Descriptions .............................................................................................................. 400
12 Watchdog Timer ............................................................................................................... 427
12.1 Block Diagram ........................................................................................................................ 428
12.2 Functional Description ............................................................................................................. 428
12.2.1 Register Access Timing ........................................................................................................... 429
12.3 Initialization and Configuration ................................................................................................. 429
12.4 Register Map .......................................................................................................................... 429
12.5 Register Descriptions .............................................................................................................. 430
13 Analog-to-Digital Converter (ADC) ................................................................................. 452
13.1 Block Diagram ........................................................................................................................ 453
February 24, 2009
Preliminary
5

5 Page





LM3S9B92 arduino
LM3S9B92 Microcontroller
List of Figures
Figure 1-1. Stellaris® LM3S9B92 Microcontroller High-Level Block Diagram ........................................ 57
Figure 2-1. CPU Block Diagram ......................................................................................................... 60
Figure 2-2. TPIU Block Diagram ........................................................................................................ 68
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 79
Figure 5-2. Test Access Port State Machine ....................................................................................... 82
Figure 5-3. IDCODE Register Format ................................................................................................. 88
Figure 5-4. BYPASS Register Format ................................................................................................ 88
Figure 5-5. Boundary Scan Register Format ....................................................................................... 88
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 91
Figure 6-2. Power Architecture .......................................................................................................... 94
Figure 6-3. Main Clock Tree .............................................................................................................. 96
Figure 7-1. Flash Block Diagram ...................................................................................................... 195
Figure 8-1. μDMA Block Diagram ..................................................................................................... 227
Figure 8-2. Example of Ping-Pong DMA Transaction ......................................................................... 233
Figure 8-3. Memory Scatter-Gather, Setup and Configuration ............................................................ 235
Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence .............................................................. 236
Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration ......................................................... 238
Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence ........................................................... 239
Figure 9-1. Digital I/O Pads ............................................................................................................. 292
Figure 9-2. Analog/Digital I/O Pads .................................................................................................. 293
Figure 9-3. GPIODATA Write Example ............................................................................................. 294
Figure 9-4. GPIODATA Read Example ............................................................................................. 294
Figure 10-1. EPI Block Diagram ......................................................................................................... 343
Figure 11-1. GPTM Module Block Diagram ........................................................................................ 389
Figure 11-2. 16-Bit Input Edge-Count Mode Example .......................................................................... 394
Figure 11-3. 16-Bit Input Edge-Time Mode Example ........................................................................... 395
Figure 11-4. 16-Bit PWM Mode Example ............................................................................................ 396
Figure 12-1. WDT Module Block Diagram .......................................................................................... 428
Figure 13-1. Implementation of Two ADC Blocks ................................................................................ 453
Figure 13-2. ADC Module Block Diagram ........................................................................................... 453
Figure 13-3. Internal Voltage Conversion Result ................................................................................. 457
Figure 13-4. External Voltage Conversion Result ................................................................................ 458
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Differential Sampling Range, VIN_ODD = 1.5 V .................................................................. 459
Differential Sampling Range, VIN_ODD = 0.75 V ................................................................ 460
Differential Sampling Range, VIN_ODD = 2.25 V ................................................................ 460
Internal Temperature Sensor Characteristic ..................................................................... 461
Figure 13-9. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ............................................................ 463
Figure 13-10. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................................. 464
Figure 13-11. High-Band Operation (CIC=0x3 and/or CTC=0x3) ............................................................ 465
Figure 14-1. UART Module Block Diagram ......................................................................................... 521
Figure 14-2. UART Character Frame ................................................................................................. 522
Figure 14-3. IrDA Data Modulation ..................................................................................................... 524
Figure 15-1. SSI Module Block Diagram ............................................................................................. 571
Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 574
Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 574
February 24, 2009
Preliminary
11

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