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PDF 74ALVCH16244 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCH16244 | |
| Descripción | LOW VOLTAGE CMOS 16-BIT BUS BUFFER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74ALVCH16244
LOW VOLTAGE CMOS 16-BIT BUS BUFFER (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
s 3.6V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED :
tPD = 3.0 ns (MAX.) at VCC = 3.0 to 3.6V
tPD = 3.7 ns (MAX.) at VCC = 2.3 to 2.7V
tPD = 5.1 ns (MAX.) at VCC = 1.65V
)s POWER DOWN PROTECTION ON INPUTS
t(sAND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
uc|IOH| = IOL = 24mA (MIN) at VCC = 3.0V
d|IOH| = IOL = 12mA (MIN) at VCC = 2.3V
ro )|IOH| = IOL = 4mA (MIN) at VCC = 1.65V
P t(ss OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V
te cs BUS HOLD PROVIDED ON DATA INPUTS
le dus PIN AND FUNCTION COMPATIBLE WITH
so ro74 SERIES 16244
s LATCH-UP PERFORMANCE EXCEEDS
b P300mA (JESD 17)
- O tes ESD PERFORMANCE:
) leHBM > 2000V (MIL STD 883 method 3015);
t(s oMM > 200V
c bsDESCRIPTION
u OThe 74ALVCH16244 is a low voltage CMOS 16
rod -BIT BUS BUFFER (NON INVERTED) fabricated
P t(s)with sub-micron silicon gate and five-layer metal
wiring C2MOS technology. It is ideal for low power
te cand very high speed 1.65 to 3.6V applications; it
le ucan be interfaced to 3.6V signal environment for
dboth inputs and outputs.
so roAny nG output control governs four BUS
b PBUFFERS. Output Enable input (nG) tied together
gives full 16-bit operation.
O teWhen nG is LOW, the outputs are enabled. When
lenG is HIGH, the output are in high impedance
ostate.
sActive bus-hold circuitry is provided to hold
Obunused or floating data inputs at a valid logic level.
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
T&R
74ALVCH16244TTR
This device is designed to be used with 3 state
memory address drivers, etc.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2003
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1 page  
74ALVCH16244
AC ELECTRICAL CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
CL RL ts = tr -40 to 85 °C
-55 to 125 °C Unit
(V) (pF) (Ω) (ns) Min. Max. Min. Max.
tPLH tPHL Propagation Delay 1.65 to 1.95 30 1000 2.0
1
5.1
1
5.1
Time
2.3 to 2.7 30 500 2.0
1
3.7
1
3.7
2.7
50 500 2.5
1
3.6
1
3.6
3.0 to 3.6 50 500 2.5
1
3.0
1
3.0
tPZL tPZH Output Enable Time 1.65 to 1.95 30 1000 2.0
1
7.1
1
7.1
2.3 to 2.7 30 500 2.0
1
5.7
1
5.7
ns
2.7
50 500 2.5
1
5.4
1
5.4
t(s)3.0 to 3.6 50 500 2.5
1
4.4
1
4.4
tPLZ tPHZ Output Disable Time 1.65 to 1.95 30 1000 2.0
1
6.5
1
6.5
c2.3 to 2.7 30 500 2.0
1
5.2
1
5.2
u2.7
50 500 2.5
1
4.6
1
4.6
rod )3.0 to 3.6 50 500 2.5
1
4.1
1
4.1
P t(s1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
lete ducCAPACITIVE CHARACTERISTICS
so roTest Condition
Value
) - Ob lete PSymbol
Parameter
VCC
(V)
TA = 25 °C
Min. Typ. Max.
Unit
t(s oCIN Input Capacitance Control
sInputs
3.3 VIN =VCC or GND
3
pF
c bCIN Input Capacitance Data Inputs
3.3
VIN =VCC or GND
6
pF
du - OCOUT Output Capacitance
3.3 VIN = 0 to VCC
7 pF
ro )CPD Power Dissipation Capacitance
P t(sOutput enabled (note 1)
te cCPD Power Dissipation Capacitance
le uOutput disabled (note 1)
3.3
2.5
3.3
2.5
fIN = 10MHz
CL=50pF
VIN = 0 or VCC
19
16
pF
5
4
d1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
so roload. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per
OObbsolete Pcircuit)
5/10
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74ALVCH16244.PDF ] | |
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