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TS25L16APP Schematic ( PDF Datasheet ) - Terra Semiconductor

Teilenummer TS25L16APP
Beschreibung 16 Mbit Serial Flash memory
Hersteller Terra Semiconductor
Logo Terra Semiconductor Logo 




Gesamt 30 Seiten
TS25L16APP Datasheet, Funktion
TS25L16APP
16 Mbit Serial Flash memory with 75 MHz
Dual and Quad SPI bus Interface
Features
Architectural Advantages
n Single power supply operation
• Full voltage range: 2.7 to 3.6 V read and
program operations
n Memory Architecture
• 32ea sectors with 512 Kb each
n Program
• Page Program (up to 256 bytes) in 0.3 ms
(typical)
• Page Write (up to 256 bytes) in 2.8 ms
(typical)
• Program cycles are on a page by page basis
n Erase
• 2ms typical Page Erase Time
• 2ms typical SubSector Erase Time
• 32ms typical Sector Erase time
• 1 sec typical Bulk Erase time
n Cycling Endurance
• 100,000 P/E cycles per sector typical
n Data Retention
• 20 years typical
n Device ID
• JEDEC standard two-byte electronic
signature
n Package Option
• Industry Standard Pin-outs
• 8-pin SOP 208 mil
• 8-pin SOP 150 mil
• 8-pin PDIP 300 mil
Performance Characteristics
n Speed
• 75 MHz clock rate (maximum)
n Dual/Quad Output Speed
• 150 MHz/300 MHz an equivalent clock rate
(maximum)
n Power Saving Standby Mode
• Standby Mode 1 µA (typical)
• Deep Power-down Mode 1 µA (typical)
Memory Protection Features
n Memory Protection
• W# (SO2) pin works in conjunction with
Status Register Bits to protect specified
memory areas
• Status Register Block Protection bits (BP3,
BP2, BP1, BP0) in status register configure
parts of memory as read-only
Software Features
n SPI Bus Compatible Serial Interface
May 2009
1/1 Terra Semiconductor






TS25L16APP Datasheet, Funktion
1. Description
TS25L16APP
The TS25L16AP device is a 3.0 Volt(2.7 V to 3.6 V) single power supply Flash memory
device. TS25L16AP consists of thirty-two sectors, each with 512 Kb memory.
Data appears on Serial Data input SI(SO0) pin when inputting data into the memory and on
Serial Data output SO(SO1) pin when outputting data from the memory. In case of Fast Read
Dual Output mode, the SI(SO0) pin becomes another output Pin and Fast Read Quad Output
mode, SI(SO0), W#(SO2) and Hold#(SO3) are used by additional outputs. The devices are
designed to be programmed in-system with the standard system 3.0 Volt VCC supply.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program, Page
Write instruction.
The memory supports Page Erase, Sub-Sector Erase, Sector Erase and Bulk Erase
instructions.
Each device requires only a 3.0 Volt power supply (2.7 V to 3.6 V) for both read and write
functions. Internally generated and regulated voltages are provided for the program
operations.
Figure 1. Logic Diagram
VCC
SI(SO0)
SCK
CS
W#(SO2)
HOLD#(SO3)
TS25L16AP
SO(SO1)
GND
Table 1. Signal names
Signal name
C = SCK
D = SI(SO0)
Q = SO(SO1)
S = CS#
W = W#(SO2)
HOLD = HOLD#(SO3)
VCC
VSS = GND
Function
Serial Clock
Serial Data input
Serial Data output
Chip Select
Write Protect
Hold
Supply voltage
Ground
Direction
Input
Input / Output
Output
Input
Input / Output
Input / Output
May 2009
6/6 Terra Semiconductor

6 Page









TS25L16APP pdf, datenblatt
4 Operating features
TS25L16APP
4.1 Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one
byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to program
all consecutive targeted bytes in a single sequence versus using several Page Program (PP)
sequences with each containing only a few bytes (see Page Program (PP), and Table 15: AC
characteristics.)
4.2 Page Erase, SubSector Erase, Sector Erase and Bulk Erase
The Page Program (PP) allows bits to be reset from 1 to 0. Before this can be applied, the bytes
of memory need to have been erased to all 1s (FFh). This can be achieved either a page,
subsector, and sector at a time, using the Page Erase (PE) , the SubSector Erase (SSE), and
the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE)
instruction. This starts an internal Erase cycle (of duration tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3 Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP or PW) or
Erase (PE, SSE, SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tpw,
tPE, tSSE, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that
the application program can monitor its value, polling it to establish when the previous Write
cycle, Program cycle or Erase cycle is complete.
May 2009
12/12
Terra Semiconductor

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