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PDF TLS203B0EJV50 Data sheet ( Hoja de datos )
| Número de pieza | TLS203B0EJV50 | |
| Descripción | Linear Voltage Post Regulator | |
| Fabricantes | Infineon Technologies | |
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TLS203B0 V50
Linear Voltage Post Regulator
Low Dropout, Low Noise, 5V, 300mA
TLS203B0EJV50
TLS203B0LDV50
Data Sheet
Rev. 1.1, 2015-01-15
Automotive Power
1 page  
3.2 Pin Definitions and Functions
TLS203B0EJV50
TLS203B0LDV50
Pin Configuration
Pin Symbol Function
1 (DSO-8 EP) Q
1,2 (TSON-10)
Output. Supplies power to the load. For this pin a minimum output capacitor of
3.3 µF is required to prevent oscillations. Larger output capacitors may be
required for applications with large transient loads in order to limit peak voltage
transients or when the regulator is applied in conjunction with a bypass capacitor.
For more details please refer to “Application Information” on Page 19.
2 (DSO-8 EP)
4 (TSON-10)
SENSE
Output Sense. The SENSE pin is the input to the error amplifier. This allows to
achieve an optimized regulation performance in case of small voltage drops Rp
that occur between regulator and load. In applications where such drops are
relevant they can be eliminated by connecting the SENSE pin directly at the load.
In standard configuration the SENSE pin can be directly connected to Q. For
further details please refer to the section “Kelvin Sense Connection” on
Page 19.
3, 7 (DSO-8 EP) NC
3, 8 (TSON-10)
No Connect. The NC Pins have no connection to any internal circuitry. Connect
either to GND or leave open.
4 (DSO-8 EP)
5 (TSON-10)
BYP
Bypass. The BYP pin is used to bypass the reference of the TLS203B0 V50 to
achieve low noise performance. The BYP-pin is clamped internally to ±0.6 V (i.e.
one VBE). A small capacitor from the output Q to the BYP pin will bypass the
reference to lower the output voltage noise 1). If not used this pin must be left
unconnected.
5 (DSO-8 EP)
7 (TSON-10)
EN
6 (DSO-8 EP)
6 (TSON-10)
GND
Enable. With the EN pin the TLS203B0 V50 can be put into a low power shutdown
state. The output will be off when the EN is pulled low. The EN pin can be driven
either by 3.3 V or 5 V logic or as well by open-collector logic with pull-up resistor.
The pull-up resistor is required to supply the pull-up current of the open-collector
gate 2) and the EN pin current 3). Please note that if the EN pin is not used it must
be connected to VI. It must not be left floating.
Ground.
8 (DSO-8 EP) I
9, 10 (TSON-10)
Input. The device is supplied by the input pin I. A capacitor at the input pin is
required if the device is more than 6 inches away from the main input filter
capacitor or if a non-negligible inductance is present at the input I 4). The
TLS203B0 V50 is designed to withstand reverse voltages on the input pin I with
respect to GND and output Q. In the case of reverse input (e.g. due to a wrongly
attached battery) the device will act as if there is a diode in series with its input. In
this way there will be no reverse current flowing into the regulator and no reverse
voltage will appear at the load. Hence, the device will protect both - the device
itself and the load.
9 (DSO-8 EP)
11 (TSON-10)
Tab
Exposed Pad. To ensure proper thermal performance, solder Pin 11 of TSON-10
to the PCB ground and tie directly to Pin 6. In the case of DSO-8 EP as well solder
Pin 9 (exposed pad) to the PCB ground and tie directly to Pin 6 (GND).
1) A maximum value of 10 nF can be used for reducing output voltage noise over the bandwidth from 10 Hz to 100 kHz.
2) Normally several microamperes.
3) Typical value is 1 µA.
4) In general the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-
powered circuits. Depending on actual conditions an input capacitor in the range of 1 to 10 µF is sufficient.
Data Sheet
5 Rev. 1.1, 2015-01-15
5 Page 
TLS203B0EJV50
TLS203B0LDV50
Electrical Characteristics
1) This parameter defines the minimum input voltage for which the device is powered up and provides the maximum nominal
output current of 300 mA. Under this minimum input voltage condition the TLS203B0 V50 starts to be in tracking mode and
the output voltage will typically be in the range of around 1 V while providing the 300 mA.
2) The operation conditions are limited by the maximum junction temperature. The regulated output voltage specification will
only apply for conditions where the limit of the maximum junction temperature is fulfilled. It will therefore not apply for all
possible combinations of input voltage and output current. When operating at maximum input voltage, the output current
must be limited for thermal reasons. The same holds true when operating at maximum output current where the input
voltage range must be limited for thermal reasons.
3) The dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output
current. In dropout, the output voltage will be equal to VI - VDR
4) GND-pin current is tested with VI = VQ,nom and a current source load. This means that this parameter is tested while being
in the dropout region. The GND pin current will in most cases decrease slightly at higher input voltages - please also refer
to the corresponding typical performance graphs.
5) The EN pin current flows into EN pin.
6) Not subject to production test, specified by design.
7) Reverse output current is tested with the I pin grounded and the Q pin forced to the rated output voltage. This current flows
into the Q pin and out of the GND pin.
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specified mean values expected over the production spread. If not otherwise specified,
typical characteristics apply at TA = 25 °C and the given supply voltage.
Data Sheet
11 Rev. 1.1, 2015-01-15
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet TLS203B0EJV50.PDF ] | |
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