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ITS41k0S-ME-N Schematic ( PDF Datasheet ) - Infineon

Teilenummer ITS41k0S-ME-N
Beschreibung Smart High-Side NMOS-Power Switch
Hersteller Infineon
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Gesamt 19 Seiten
ITS41k0S-ME-N Datasheet, Funktion
ITS41k0S-ME-N
Smart High-Side NMOS-Power Switch
Data Sheet
Rev 1.0, 2012-09-01
Standard Power






ITS41k0S-ME-N Datasheet, Funktion
4.2 Functional Range
ITS41k0S-ME-N
General Product Characteristics
Table 2 Functional Range
Parameter
Symbol
Nominal Operating Voltage VS
Min.
4.9
Values
Typ. Max.
– 60
Unit
V
Note /
Test Condition
VS increasing
Number
4.2.1
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3 Thermal Resistance
This thermal data was generated in accordance with JEDEC JESD51 standards.
More information on www.jedec.org.
Table 3 Thermal Resistance1)
Parameter
Symbol
Values
Unit Note /
Number
Min. Typ. Max.
Test Condition
PG-SOT223-4
Junction to Case, Exposed pad
Junction to ambient
Rthjc
RthJA_1s0p
– 40.5 –
– 145.4 –
K/W
K/W
2)
4.3.1
4.3.2
Junction to ambient
Junction to ambient
Junction to ambient
Junction to ambient
RthJA_1s0p_300mm
RthJA_1s0p_600mm
RthJA_2s2p
RthJA_2s2pvia
77.2 –
66.2 –
57.8 –
52.9 –
K/W
K/W
K/W
K/W
3)
4)
5)
6)
4.3.3
4.3.4
4.3.5
4.3.6
1) Not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, footprint; the Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu.
3) Specified RthJA value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, Cu, 300mm2; the Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu.
4) Specified RthJA value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, 600mm2; the Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu.
5) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
6) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board with two thermal
vias; the Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm
Cu, 2 x 35µm Cu. The diameter of the two vias are equal 0.3mm and have a plating of 25um with a copper heatsink area
of 3mm x 2mm). JEDEC51-7: The two plated-through hole vias should have a solder land of no less than 1.25 mm
diameter with a drill hole of no less than 0.85 mm diameter.
Data Sheet
6 Rev 1.0, 2012-09-01

6 Page









ITS41k0S-ME-N pdf, datenblatt
6.4 Protection behavior
ITS41k0S-ME-N
Application Information
Overtemperature concept:
ON
TjRestart
TjTrip
heating
up
Overtemperature behavior
IIN
0
IINON
IINOFF
VOUT
t
OFF
Device
Status
Normal
cooling
down
THYS
Toggling
TJ
Overtemperature
0
Tj
TjTrip
t
THYS
OFF ON
OFF
ON
t
OFF
Waveforms turn on into a short circuit :
IIN
0
VOUT
IINON
IINOFF
t
Waveforms short circuit during on state :
IIN
0
VOUT
IINON
IINOFF
t
0
t
IL
ILSCR
0
ILSCP
tM
tSCOFF
Ipeak
Controlled
by the
current limit
circuit
t
OFF Overloaded
OFF
Shut down by overtemperature and
restart by cooling (toggling )
0
IL
ILSCR
t
Ipeak
Controlled
by the
current limit
circuit
0
OFF
Normal
operation
OUT shorted to GND
Shut down by overtemperature and
restart by cooling (toggling )
t
Figure 7 Protective behaviour waveforms of the ITS41k0S-ME-N
Data Sheet
12 Rev 1.0, 2012-09-01

12 Page





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