PDF ADF5904 Data sheet ( Hoja de datos )

Número de pieza	ADF5904
Descripción	Receiver Downconverter
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet 4-Channel, 24 GHz, Receiver Downconverter ADF5904 FEATURES GENERAL DESCRIPTION Integrated baluns for single-ended receiver (Rx) inputs and local oscillator (LO) input Rx channel gain: 22 dB Noise figure (NF): 10 dB P1dB: −10 dBm LO input range: −8 dBm to +5 dBm Rx to IF isolation: 30 dB RF signal bandwidth: 250 MHz Rx output impedance: 900 Ω differential LO input buffer: 24 GHz RF and LO S11 at 50 Ω: −5 dB Temperature sensor with analog output: ±5° Electric static distortion (ESD) performance Human body model (HBM): 1000 V Charged device model (CDM): 500 V Qualified for automotive applications The ADF5904 is a 4-channel, 24 GHz, receiver downconverter. Each channel contains a single-ended RF input with an on-chip balun followed by a differential low noise amplifier (LNA) and a downconverter mixer with differential output buffers. The RF LO path also has an on-chip balun. Control of the on-chip registers is through a simple 3-wire interface. The ADF5904 comes in a compact 32-lead, 5 mm × 5 mm LFCSP package. APPLICATIONS Automotive radars Industrial radars Microwave (µW) radar sensors FUNCTIONAL BLOCK DIAGRAM AVDD RX1_RF RX2_RF RX3_RF RX4_RF ATEST CE CLK DATA LE DOUT TEMP SENSOR 32-BIT DATA REGISTER BALUN LNA BALUN LNA BALUN LNA BALUN LNA LO_IN BALUN ADF5904 GND Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND Digital Input/Output Voltage to GND Analog Input/Output Voltage to GND RXx_RF, LO_IN to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature θJA Thermal Impedance1 (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Transistor Count CMOS Bipolar ESD CDM HBM Rating –0.3 V to +3.9 V –0.3 V to AVDD + 0.3 V –0.3 V to AVDD + 0.3 V –0.3 V to AVDD + 0.3 V –40°C to +105°C –65°C to +125°C 150°C 40.83°C/W 260°C 40 sec 65,100 2280 500 V 1000 V 1 Two signal planes (that is, on the top and the bottom surfaces of the board), two buried planes, and nine vias. ADF5904 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. 0 \| Page 5 of 15 5 Page Data Sheet REGISTER 0 (R0) ADF5904 RESERVED RESERVED CONTROL BITS DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 10 0 00 0 0 0000 000 0 0 0 PC4 PC3 PC2 PC1 PLO LPB DIO 1 0 1 0 0 0 C2(0) C1(0) PC4 PUP CH4 0 POWER DOWN 1 POWER UP PC3 PUP CH3 0 POWER DOWN 1 POWER UP PC2 PUP CH2 0 POWER DOWN 1 POWER UP PC1 PUP CH1 0 POWER DOWN 1 POWER UP PLO PUP LO 0 POWER DOWN 1 POWER UP DIO DOUT VSEL 0 3.3V 1 1.8V LPB 0 1 LO_IN PIN BIAS NO DC BIAS 1.5V DC BIAS Figure 18. Register 0 REGISTER 0 Register 0 Control Bits With Bits[C2:C1] set to 00, Register R0 is programmed. Figure 18 shows the input data format for programming this register. DOUT VSEL DB8 controls the DOUT logic levels. Set this bit to 0 to set the DOUT logic level to 3.3 V, and set this bit to 1 to sets the DOUT logic level to 1.8 V. LO_IN Pin Bias DB9 controls the dc bias voltage on the LO_IN pin (Pin 29). Set this bit to 0 to set no dc bias on the LO_IN pin, and set this bit to 1 to set the dc bias to 1.5 V. AC couple the LO signal to the LO_IN pin. PUP LO DB10 provides the power-up bit for the LO block. Set this bit to 0 to power down the LO block, and set this bit to 1 to return the LO block to normal operation. PUP CH1 DB11 provides the power-up bit for RF Receiver Channel 1. Setting this bit to 0 performs a power-down of Channel 1 blocks. Setting this bit to 1 returns Channel 1 blocks to normal operation. PUP CH2 DB12 provides the power-up bit for RF Receiver Channel 2. Set this bit to 0 to power down the Channel 2 blocks, and set this bit to 1 to return the Channel 2 blocks to normal operation. PUP CH3 DB13 provides the power-up bit for RF Receiver Channel 3. Set this bit to 0 to power down the Channel 3 blocks, and set this bit to 1 to return the Channel 3 blocks to normal operation. PUP CH4 DB14 provides the power-up bit for RF Receiver Channel 4. Set this bit to 0 to power down the Channel 4 blocks, and set this bit to 1 to return the Channel 4 blocks to normal operation. Rev. 0 \| Page 11 of 15 11 Page

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