PDF K4A4G165WD Data sheet ( Hoja de datos )

Número de pieza	K4A4G165WD
Descripción	4Gb D-die DDR4 SDRAM
Fabricantes	Samsung
Logotipo
Hay una vista previa y un enlace de descarga de K4A4G165WD (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! Rev. 0.5, Feb. 2014 K4A4G165WD Preliminary 4Gb D-die DDR4 SDRAM x16 only 96FBGA with Lead-Free & Halogen-Free (RoHS compliant) 1.2V CAUTION : This document includes some items still under discussion in JEDEC. Therefore, those may be changed without pre-notice based on JEDEC progress. In addition, it is highly recommended that you not send specs without Samsung’s permission. datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. (C) 2014 Samsung Electronics Co., Ltd. All rights reserved. -1- 1 page K4A4G165WD datasheet 3. Package pinout/Mechanical Dimension & Addressing 3.1 x16 Package Pinout (Top view) : 96ball FBGA Package Preliminary Rev. 0.5 DDR4 SDRAM 1 2 3 456 7 8 9 A VDDQ VSSQ DQU0 B VPP VSS VDD C VDDQ DQU4 DQU2 D VDD VSSQ DQU6 E VSS DMU_n/ DBIU_n VSSQ F VSSQ VDDQ DQSL_c G VDDQ DQL0 DQSL_t H VSSQ DQL4 DQL2 J VDD VDDQ DQL6 K VSS CKE ODT L VDD WE_n/ A14 ACT_n M VREFCA BG0 A10/AP N VSS BA0 A4 P RESET_n A6 A0 R VDD A8 A2 T VSS A11 PAR DQSU_c DQSU_t DQU3 DQU7 DML_n DBIL_n DQL1 VDD DQL3 DQL7 CK_t VSSQ DQU1 DQU5 VSSQ VSSQ VDDQ VSS DQL5 VDDQ CK_c VDDQ VDD VSSQ VDDQ VSS ZQ VDDQ VSSQ VDD VSS CS_n RAS_n VDD A12/BC_n A3 A1 A9 NC CAS_n BA1 A5 A7 A13 VSS TEN ALERT_n VPP VDD A B C D E F G H J K L M N P R T Ball Locations (x16) Populated ball Ball not populated Top view (See the balls through the package) 123456789 A B C D E F G H J K L M N P R T -5- 5 Page K4A4G165WD datasheet Preliminary Rev. 0.5 DDR4 SDRAM 8. AC & DC Input Measurement Levels 8.1 AC & DC Logic input levels for single-ended signals [ Table 6 ] Single-ended AC & DC input levels for Command and Address Symbol Parameter DDR4-1600/1866/2133/2400 Min. Max. VIH.CA(DC75) DC input logic high VREFCA+ 0.075 VDD VIL.CA(DC75) DC input logic low VSS VREFCA-0.075 VIH.CA(AC100) AC input logic high VREF + 0.1 Note 2 VIL.CA(AC100) AC input logic low Note 2 VREF - 0.1 VREFCA(DC) Reference Voltage for ADD, CMD inputs 0.49VDD 0.51VDD NOTE : 1. See “Overshoot and Undershoot Specifications” . 2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV) 3. For reference : approx. VDD/2 ± 12mV Unit NOTE V V V1 V1 V 2,3 8.2 VREF Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA is illustrated in Figure 1. It shows a valid reference voltage VREF(t) as a func- tion of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 6 on page 12. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD. voltage VDD VSS Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits time The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. "VREF" shall be understood as VREF(DC), as defined in Figure 1 . This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings. - 12 - 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet K4A4G165WD.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
K4A4G165WD	4Gb D-die DDR4 SDRAM	Samsung

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar