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PDF PL102-10 Data sheet ( Hoja de datos )
| Número de pieza | PL102-10 | |
| Descripción | Low Skew Output Buffer | |
| Fabricantes | Micrel | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PL102-10 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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FE AT UR E S
Frequency Range:
− 15 to 170MHz @ 3.3V
− 15 to 145MHz @ 2.5V
Internal Phase Locked Loop Allows Spread
Spectrum Modulation on Reference Clock to
Pass to Outputs.
Zero Input to Output Delay
Less Than 700ps Device to Device Skew
Less Than 200ps Skew Between Outputs
Less Than 100ps Cycle to Cycle Jitter
2.5V or 3.3V Power Supply
Available in 8-Pin SOP or 6-pin SOT GREEN/ RoHS
Compliant Packages
PL102-10
Low Skew Output Buffer
PIN CONFIGURATION
REFIN 1
8 CLKOUT
GND 2
7 DNC
CLK1 3
6 DNC
CLK2 4
5 VDD
SOP-8L
CLK1 1 6 CLK2
GND 2 5 VDD
REFIN 3 4 CLKOUT
SOT23-6L
DESCRIPTION
The PL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed
clocks and is available in 8-pin SOP or 6-pin SOT23 package. It has two outputs that are synchronized with the
input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between
the input and output is less than 350 ps, the device acts as a zero delay buffer.
BLOCK DIAGRAM
REFIN
PLL
CLKOUT
CLK1
CLK2
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/5/09 Page 1
1 page  
PL102-10
Low Skew Output Buffer
Output-Output Skew
The skew between CLKOUT and the CLK(1-2) outputs is not dynamically adjusted by the
PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained
from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will be
maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must be equally loaded.
If the CLK(1-2) outputs are less loaded than CLKOUT, CLK(1-2) outputs will lead it; if the
CLK(1-2) is more loaded than CLKOUT, CLK(1-2) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-2) outputs are identical, they all start at the same time,
but difference loads cause them to have different rise times and different times crossing
the measurement thresholds.
REF
CLKOUT
CLK(1-2)
Zero Delay
REF input and all outputs are equally loaded
REF
CLKOUT
CLK(1-2)
Advanced
REF input and CLK(1-2) outputs are equally loaded,
with CLK(1-2) less loaded than CLKOUT.
REF
CLKOUT
CLK(1-2)
Delayed
REF input and CLK(1-2) outputs loaded equally,
withCLK(1-2) more loaded then CLKOUT.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/5/09 Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PL102-10.PDF ] | |
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