PDF ADN2915 Data sheet ( Hoja de datos )

Número de pieza	ADN2915
Descripción	Continuous Rate 6.5 Mbps to 11.3 Gbps Clock and Data Recovery IC
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Continuous Rate 6.5 Mbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ ADN2915 FEATURES GENERAL DESCRIPTION Serial data input: 6.5 Mbps to 11.3 Gbps No reference clock required Exceeds SONET/SDH requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 7.3 mV typical (limiting amplifier mode) Optional limiting amplifier, equalizer, and bypass inputs Programmable jitter transfer bandwidth to support G.8251 OTN Programmable slice level Sample phase adjust (5.65 Gbps or greater) Output polarity invert Programmable LOS threshold via I2C I2C to access optional features The ADN2915 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automati- cally locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance. The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer, or bypass at the input. The equalizer is either adaptive or can be manually set. Loss of signal (LOS) alarm (limiting amplifier mode only) The receiver front-end loss of signal (LOS) detector circuit Loss of lock (LOL) indicator indicates when the input signal level has fallen below a user- PRBS generator/detector Application-aware power 430 mW at 11.3 Gbps, equalizer enabled, no clock output 380 mW at 6.144 Gbps, limiting amplifier mode, no clock output 340 mW at 622 Mbps, input bypass mode, no clock output Power supply: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V 4 mm × 4 mm 24-lead LFCSP APPLICATIONS SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all associated FEC rates programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers. The ADN2915 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2915 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted. 1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE WDM transponders Any rate regenerators/repeaters FUNCTIONAL BLOCK DIAGRAM SCK SDA LOL REFCLKP/ REFCLKN (OPTIONAL) DATOUTP/ DATOUTN CLKOUTP/ CLKOUTN I2C_ADDR I2C REGISTERS FREQUENCY ACQUISITION AND LOCK DETECTOR DATA RATE ADN2915 CML CML CLK DDR LOS LOS DETECT SAMPLE PHASE ADJUST FIFO ÷N ÷2 PIN NIN 50Ω 2 50Ω LA BYPASS EQ DATA INPUT SAMPLER RXD RXCK DOWNSAMPLER AND LOOP FILTER DCO CLOCK I2C I2C PHASE SHIFTER VCM VCC FLOAT Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet ADN2915 JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data pattern: PRBS 223 − 1, ac-coupled to 100 Ω differential termination load, I2C register default settings, unless otherwise noted. Table 2. Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer Bandwidth (BW)1 OC-192 8GFC3 OC-48 OC-12 OC-3 Jitter Peaking OC-192 8GFC3 OC-48 OC-12 OC-3 Jitter Generation OC-192 8GFC3 OC-48 OC-12 OC-3 Jitter Tolerance OC-192 8GFC,3 JTSPAT Sinusoidal Jitter at 340 kHz Sinusoidal Jitter at 5.098 MHz Sinusoidal Jitter at 80 MHz Rx Jitter Tracking Test4 510 kHz, 1 UI 100 kHz, 5 UI Test Conditions/Comments Min Typ TRANBW[2:0] = 3 OTN mode,2 TRANBW[2:0] = 1 TRANBW[2:0] = 4 (default) OTN mode,2 TRANBW[2:0] = 1 1064 294 1242 663 157 175 44 20 kHz to 80 MHz 20 kHz to 80 MHz 20 kHz to 10 MHz 0.014 0.004 0.004 0.01 0.01 Unfiltered Unfiltered Unfiltered Unfiltered 12 kHz to 20 MHz Unfiltered 12 kHz to 20 MHz Unfiltered 12 kHz to 5 MHz Unfiltered 12 kHz to 5 MHz Unfiltered 12 kHz to 1.3 MHz Unfiltered 12 kHz to 1.3 MHz Unfiltered TRANBW[2:0] = 4 (default) 2000 Hz 20 kHz 400 kHz 4 MHz 80 MHz 0.0045 0.076 0.005 0.044 0.0025 0.0156 0.0007 0.0038 0.0002 0.0008 4255 106 3.78 0.46 0.42 Voltage modulation amplitude (VMA) = 170 mV p-p at 100 MHz, 425 mV p-p at 100 MHz, 170 mV p-p at 2.5 GHz, and 425 mV p-p at 2.5 GHz excitation frequency5 10−12 10−12 6.7 0.53 0.59 <10−12 <10−12 Max Unit 1650 529 1676 896 181 kHz kHz kHz kHz kHz kHz kHz 0.024 0.021 0.023 dB dB dB dB dB 0.0067 0.0046 0.0276 0.0011 0.0076 0.0003 0.0018 UI rms UI p-p UI rms UI p-p UI rms UI rms UI p-p UI p-p UI rms UI rms UI p-p UI p-p UI rms UI rms UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p BER BER Rev. 0 \| Page 5 of 36 5 Page Data Sheet ADN2915 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VCC = 1.2 V, VCC1 = 1.8 V, VDD = 3.3 V, VEE = 0 V, input data pattern: PRBS 215 − 1, ac-coupled inputs and outputs, unless otherwise noted. 16.8ps/DIV Figure 6. Output Eye Diagram at OC-192 1k ADN2915 TOLERANCE 100 10 1 SONET REQUIREMENT MASK 0.1 0.01 100 1k 100 1k 10k 100k 1M 10M JITTER FREQUENCY (Hz) Figure 7. Jitter Tolerance: OC-192 100M ADN2915 EQUIPMENT LIMIT SONET MASK 10 1 0.1 10 100 1k 10k 100k 1M 10M 100M JITTER FREQUENCY (Hz) Figure 8. Jitter Tolerance: OC-48 66.9ps/DIV Figure 9. Output Eye Diagram at OC-48 5 XFP MASK 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 10. Jitter Transfer: OC-192 (TRANBW[2:0] = 3) 5 SONET MASK 0 –5 –10 –15 –20 –25 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 11. Jitter Transfer: OC-48 100M Rev. 0 \| Page 11 of 36 11 Page

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