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PDF ML610Q384 Data sheet ( Hoja de datos )
| Número de pieza | ML610Q384 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
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ML610Q380/ML610Q383
FEDL610Q380FULL-01
Issue Date: Mar 9, 2012
ML610Q384/ML610Q385
8-bit Microcontroller with Voice Output Function
I
GENERAL DESCRIPTION
Equipped with a 8-bit CPU nX-U8/100, the ML610Q380/383/384/385 is a high-performance 8-bit CMOS
microcontroller that integrates a wide variety of peripherals such as 12-bit A/D converter, timer, PWM,
synchronous serial port, UART, I２C bus interface (master), Battery level detect circuit, LCD driver, voice output
function and speaker amplifier. The nX-U8/100 CPU is capable of executing instructions efficiently on a
one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture.
In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI
mounted on the board.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system:16-bit instructions
− Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 μs (at 32.768kHz system clock)
Approx 0.122 μs (at 8.192MHz system clock)＠DVDD = 2.2 to 5.5V
• Internal memory
− Has 128-Kbyte flash ROM(64K × 16-bit) built in. (1K byte of test domain that it cannot be used is
included)
− Has 2-Kbyte RAM (2048 × 8 bits) built in.
− Has maximum of 16-Mbit P2ROM (only ML610Q383/384/385)
P2ROM capacity: ML610Q383 (4M bit), ML610Q384 (8M bit), and ML610Q385 (16M bit)
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 24 maskable interrupt sources (Internal source: 20, External source: 4)
• Time base counter
− Low-speed time base counter × 1 channel
− High-speed time base counter × 1 channel
• Watchdog timer
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 6ch (16-bit configuration available)
1/29
1 page  
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Block diagram of ML610Q383/384/385
Figure 1-2 is a block diagram of the ML610Q383/384/385.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port.
EPSW1～3
PSW
Timing
Controller
On-Chip
ICE
CPU (nX-U8/100) Large
GREG d ELR1～3
0～15
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
DVVDSDS
Data-bus
RESET_N
TEST0
TEST1_N
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
RESET &
TEST
OSC
INT
1
VDDL
VDDR
POWER
SG
AOUT
VOICECNT
INT
1
SSPPVVDSDS
SPP
SPM
SG
SPIN
VVDSDS
VREF
AIN0 to AIN3*3
SPEAKER
AMP
10bit-ADC
INT
1
PVPP AIN4 to AIN7＊3
PSO
PSCK
16Mbit PSI
P2ROM PCSB
*1 P50(SIN1)
*1 P51(SCK1) GPIO
*1 P52(SOUT1)
*1 P53
INT
4
INT
6
INT
RAM
2048byte
Interrupt
Controller
TBC
8bit Timer
×6
WDT
BLD
*1 Secondary or tertiary function
*2 Select I/O port or LCD driver
*3 Select I/O port or A/D converter input
*4 For P2ROM
ECSR1～3
DSR/CSR
PC
BUS
Controller
Program
Memory
（Flash）
128Kbyte
INT
2
SSIO
INT
2
UART
INT
1
I2C
INT
2
PWM
INT
5
GPIO
LCD
Driver
LCD
Drive Voltage
VPP
SCK0*1, SCK1*4
SIN0*1, SIN1*4
SOUT0*, SOUT1*4
RXD0*1, RXD1*1
TXD0*1, TXD1*1
SDA*1
SCL*1
PPWWMM45**11
PW45EV0*1
PW45EV1*1
NMI
P00 to P03
P10 to P11
P20 to P23
P30 to P33*3
P34 to P35
P40 to P43
P44 to P47*3
PC0 to PC7*2
PD0 to PD7*2
COM0 to COM3
SEG0 to SEG7
SEG8 to SEG23*2
VL1, VL2, VL3
5/29
5 Page 
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Supplementation: Only ML610Q383/384/385. ( ML610Q380 doesn't correspond.)
P50 to P53 is connected with building P2ROM by the inside of the chip into,
and each function exists.
(The external pin name becomes TESTO0 to TESTO3. Please give the external terminal processing to
me as an opening.)
Connected with P2ROM content is shown as follows.
The pins of built-in P2ROM
PSO
PSCK
PSI
PCSB
Explanation
Serial-data output
connected with P50/SIN1 (Tertiary functional) inside.
Serial-data output
connected with P51/SCK1 (Tertiary functional) inside
Serial-data input
connected with P52/SOUT1 (Tertiary functional) inside
Chip select input
connected with P53 (Primary functional) inside
11/29
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ML610Q384.PDF ] | |
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