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PDF ML610Q475 Data sheet ( Hoja de datos )

Número de pieza ML610Q475
Descripción 8-bit Microcontroller
Fabricantes LAPIS Semiconductor 
Logotipo LAPIS Semiconductor Logotipo



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No Preview Available ! ML610Q475 Hoja de datos, Descripción, Manual

ML610Q474/ML610Q475/ML610Q476
8-bit Microcontroller with a Built-in LCD driver
FEDL610Q476-02
Issue Date Jul. 31, 2014
GENERAL DESCRIPTION
This LSI is a high performance CMOS 8-bit microcontroller equipped with an 8-bit CPU nX-U8/100 and integrated with
peripheral functions such as the UART, melody driver, Analog compartor, and LCD driver.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel processing. Additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits
leak current at high temperatures, and is most suitable for battery-driven applications.
MTP version can rewrite programs on-board, which can contribute to reduction in product development TAT. The flash
memory incorporated into this MTP version implements the mask ROM-equivalent low-voltage operation (1.25V or higher)
and low-power consumption (typically 4.5uA at low-speed operation), enabling volume production by the MTP version.
FEATURES
CPU
- 8-bit RISC CPU (CPU name: nX-U8/100)
- Instruction system: 16-bit length instruction
- Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
- On-Chip debug function
- Minimum instruction execution time
30.5 µs (@ 32.768 kHz system clock)
2 µs (@ 500 kHz system clock)
0.5 µs (@ 2 MHz system clock)
Internal memory
- Internal 16KByte flash memory (8K x 16 bits) (including unusable 1K Byte TEST area)
- Internal 1KByte RAM (1024 x 8 bits)
Interrupt controller
- 1 non-maskable interrupt source:
Internal source: 1 (Watchdog Timer)
- 22 maskable interrupt sources:
Internal source: 12 (Timer0, Timer1, Timer 2, Timer 3, Timer C, Timer D, UART0, TBC128Hz, TBC32Hz, TBC16Hz,
TBC2Hz, Analog Comparator)
External source: 10 (P00, P01, P02, P03, P50, P51, P52, P53, P54, P56)
(One interrupt request is generated from P50 to P54, P56 interrupt sources.)
Time base counter
- Low-speed time base counter x 1 channel
Frequency compensation (Compensation range: Approx. -488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
- High-speed time base counter x 1 channel
Watchdog timer
- Non-maskable interrupt and reset
- Free running
- Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s)

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ML610Q475 pdf
PIN CONFIGURATION
ML610Q474 Chip Pad Layout & Dimension
FEDL610Q476-02
ML610Q474/ML610Q475/ML610Q476
P67 57
P66 58
P65 59
P64 60
P63 61
P62 62
P61 63
P60 64
P53 65
P52 66
P51 67
P50 68
P42 69
P43 70
VSS 71
P20 72
P21 73
VPP 74
37 SEG10
36 SEG9
35 SEG8
34 SEG7
33 SEG6
32 SEG5
31 SEG4
30 SEG3
29 COM4/SEG2
28 COM3/SEG1
27 COM2/SEG0
26 COM1
25 COM0
24 VL3
23 VL2
22 VL1
21 C2
20 C1
2.23mm
y
x
Chip size: 2.23mm ×2.10mm
PAD count: 74 pins
Minimum PAD pitch: 80µm
PAD aperture: 70µm×70µm
Chip thickness: 350µm
Voltage of the rear side of chip: VSS level.
Figure 5 ML610Q474 Chip Pin Layout & Dimension
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ML610Q475 arduino
FEDL610Q476-02
ML610Q474/ML610Q475/ML610Q476
PIN PAD
Primary function
No. No.
Pin name
I/O
Function
27 25
COM0
O LCD common pin
28 26
COM1
O LCD common pin
29 27 COM2/SEG0 O LCD common/segment pin
30 28 COM3/SEG1 O LCD common/segment pin
31 29 COM4/SEG2 O LCD common/segment pin
32 30
SEG3
O LCD segment pin
33 31
SEG4
O LCD segment pin
34 32
SEG5
O LCD segment pin
35 33
SEG6
O LCD segment pin
36 34
SEG7
O LCD segment pin
37 35
SEG8
O LCD segment pin
38 36
SEG9
O LCD segment pin
39 37
SEG10
O LCD segment pin
41 38
SEG11
O LCD segment pin
42 39
SEG12
O LCD segment pin
43 40
SEG13
O LCD segment pin
44 41
SEG14
O LCD segment pin
45 42
SEG15
O LCD segment pin
46 43
SEG16
O LCD segment pin
47 44
SEG17
O LCD segment pin
48 45
SEG18
O LCD segment pin
49 46
SEG19
O LCD segment pin
50 47
SEG20
O LCD segment pin
51 48
SEG21
O LCD segment pin
52 49
SEG22
O LCD segment pin
53 50
SEG23
O LCD segment pin
54 51
SEG24
O LCD segment pin
55 52
SEG25
O LCD segment pin
56 53
SEG26
O LCD segment pin
57 54
SEG27
O LCD segment pin
58 55
SEG28
O LCD segment pin
59 56
SEG29
O LCD segment pin
62
57
P67(*2)
O Output port
SEG30(*3) (*4) O LCD segment pin
63
58
P66(*2)
O Output port
SEG31(*3) (*4) O LCD segment pin
64
59
P65(*2)
SEG32(*3) (*4)
O Output port
O LCD segment pin
65
60
P64(*2)
O Output port
SEG33(*3) (*4) O LCD segment pin
66 61
P63(*2) (*3)
SEG34(*4)
O Output port
O LCD segment pin
67 62
P62(*2) (*3)
SEG35(*4)
O Output port
O LCD segment pin
68 63
P61(*2) (*3)
SEG36(*4)
O Output port
O LCD segment pin
69 64
P60(*2) (*3)
SEG37(*4)
O Output port
O LCD segment pin
Pin name
Secondary function
I/O Function
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
(*1) Internally generated, or connect to either positive power supply pin (VDD) or power supply pin for internal logic (VDDL).
For details, see user’s manual.
(*2) Pad for ML610Q474.
(*3) Pad for ML610Q475.
(*4) Pad for ML610Q476.
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