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PDF ML610Q485 Data sheet ( Hoja de datos )
| Número de pieza | ML610Q485 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
| Logotipo |  |
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ML610Q485
8-bit Microcontroller
FEDL610Q485-01
Issue Date Aug. 25, 2014
GENERAL DESCRIPTION
This LSI is a high performance CMOS 8-bit microcontroller equipped with an 8-bit CPU nX-U8/100 and integrated with
peripheral functions such as synchronous serial port, UART, melody driver, and Analog compartor.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel processing. Additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits
leak current at high temperatures, and is most suitable for battery-driven applications.
MTP version can rewrite programs on-board, which can contribute to reduction in product development TAT. The flash
memory incorporated into this MTP version implements the mask ROM-equivalent low-voltage operation (1.25V or higher)
and low-power consumption (typically 5uA at low-speed operation), enabling volume production by the MTP version. For
industrial use, ML610Q485P with the extended operating ambient temperature ranging from -40°C to 85°C are available.
FEATURES
• CPU
- 8-bit RISC CPU (CPU name: nX-U8/100)
- Instruction system: 16-bit length instruction
- Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
- On-Chip debug function
- Minimum instruction execution time
30.5 μs (@ 32.768 kHz system clock)
2 μs (@ 500 kHz system clock)
0.25 μs (@ 4 MHz system clock)
• Internal memory
- Internal 32KByte flash memory (16K x 16 bits) (including unusable 1K Byte TEST area)
- Internal 2KByte RAM (2048 x 8 bits)
• Interrupt controller
- 1 non-maskable interrupt source:
Internal source: 1 (Watchdog Timer)
- 28 maskable interrupt sources:
Internal source: 16 (SSIO0, Timer0, Timer1, Timer 2, Timer 3, Timer C, Timer D, UART0, Melody 0, PWM0,
TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz, Analog Comparator, RTC)
External source: 12 (P00, P01, P02, P03, P50, P51, P52, P53, P54, P55, P56, P57)
(One interrupt request is generated from P50 to P57 interrupt sources.)
• Time base counter
- Low-speed time base counter x 1 channel
Frequency compensation (Compensation range: Approx. -488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
- High-speed time base counter x 1 channel
• Real time clock
− Year, month, day, hour, minute, and second registers
− Adjustable to compensate for crystal variations
− Automatic leap year correction
− Regular interrupts (0.5 sec, 1 sec, 1 minute)
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1 page  
CHIP PAD LAYOUT
ML610Q485 Chip Pad Layout & Dimension
FEDL610Q485-01
ML610Q485
P47 33
P46 34
P45 35
P44 36
P57 37
P56 38
P55 39
P54 40
2.00mm
20 P53
19 P52
18 P51
17 P50
16 P03
15 P02
14 P01
13 P00
y
x
Chip size: 2.00mm × 2.08mm
PAD count: 40 pins
Minimum PAD pitch: 80μm
PAD aperture: 70μm×70μm
Chip thickness: 350μm
Voltage of the rear side of chip: VSS level.
Figure 2 ML610Q485 Chip Pin Layout & Dimension
5/25
5 Page 
FEDL610Q485-01
ML610Q485
Pin name I/O
Description
Primary/
Secondary/
Tertiary
Logic
Melody
MD0
PWM
PWM0
T02P0CK
O Melody/buzzer signal output pin. This pin is used as the secondary Secondary Positive/
function of the P50 pin.
negative
O PWM0 output pin. This pin is used as the tertiary function of the
P43 pin.
I PWM0 external clock input pin. This pin is used as the primary
function of the P44 pin.
Tertiary
Primary
Positive
—
Analog Comparator
CMPP0
I Analog comparator noninverting input0 pin. This pin is used as the
primary function of the P54.
Primary
—
CMPP1
I Analog comparator noninverting input1 pin. This pin is used as the
primary function of the P55.
Primary
—
CMPM0
I Analog comparator inverting input0 pin. This pin is used as the
primary function of the P56.
Primary
—
CMPM1
I Analog comparator inverting input1 pin. This pin is used as the
primary function of the P57.
Primary
—
Test
TEST0
I/O Pin for testing. A pull-down resistor is internally connected.
— Positive
TEST1_N
I Pin for testing. A pull-up resistor is internally connected.
— Negative
Power supply
VSS — Negative power supply pin.
——
VDD — Positive power supply pin.
——
VHF — Positive power supply pin (internally generated) for Halver.
——
Capacitor CHF (see measuring circuit 1) should be connected
between this pin and VSS.
VDDL
VDDX
CH1
CH2
VPP
— Positive power supply pin (internally generated) for internal logic.
Capacitors CL (see measuring circuit 1) are connected between this
pin and VSS.
— Positive power supply pin (internally generated) for low-speed
oscillation.
Capacitor CX (see measuring circuit 1) should be connected
between this pin and VSS.
— Capacitor connection pin for halver circuit.
—
Capacitor CH12 (see measuring circuit 1) are connected between
CH1 and CH2.
— Power supply pin for programming Flash ROM. A pull-down resistor
is internally connected.
—
—
—
—
—
—
—
—
—
—
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