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PDF LM9801 Data sheet ( Hoja de datos )
| Número de pieza | LM9801 | |
| Descripción | 8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1996
LM9801 8-Bit Greyscale 24-Bit Color Linear
CCD Sensor Processor
General Description
The LM9801 is a high performance integrated signal proc-
essor digitizer for linear CCD image scanners The LM9801
performs all the analog processing (correlated double sam-
pling for black level and offset compensation pixel-by-pixel
gain (shading) correction and 8-bit analog-to-digital conver-
sion) necessary to maximize the performance of a wide
range of linear CCD sensors
The LM9801 can be digitally programmed to work with a
wide variety of CCDs from different manufacturers An inter-
nal configuration register sets CCD and sampling timing to
maximize performance simplifying the design and manufac-
turing processes
The LM9801 can be used with parallel output color CCDs A
signal inversion mode eases use with CIS sensors For com-
plementary voltage reference see the LM4041
Applications
Y Color and Greyscale Flatbed and Sheetfed Scanners
Y Fax and Multifunction Peripherals
Y Digital Copiers
Y General Purpose Linear CCD Imaging
Features
Y 2 5 Million pixels s conversion rate
Y Pixel-rate shading correction for individual pixels maxi-
mizes dynamic range and resolution even on ‘‘weak’’
pixels
Y Implements Correlated Double Sampling for minimum
noise and offset error
Y Reference and signal sampling points digitally con-
trolled in 25 ns increments for maximum performance
Y Generates all necessary CCD clock signals
Y Compatible with a wide range of linear CCDs
Y Supports some Contact Image Sensors (CIS)
Y TTL CMOS input output compatible
Key Specifications
Y Resolution
8 Bits
Y Pixel Conversion Rate
2 5 MHz
Y Supply Voltage
a5V g 5%
Y Supply Voltage (Digital I O)
a3 3V g 10% or a5V g 5%
Y Power Dissipation
230 mW (max)
Connection Diagrams
TL H 12814 – 1
Ordering Information
Commercial (0 C s TA s a70 C)
LM9801CCV
LM9801CCVF
Package
V52A 52-Pin Plastic Leaded Chip Carrier
VEG52A 52-Pin Thin Quad Flatpack
TL H 12814 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRETM is a trademark of National Semiconductor Corporation
SPITM is a trademark of Motorola Inc
C1996 National Semiconductor Corporation TL H 12814
RRD-B30M96 Printed in U S A
http www national com
1 page  
DC and Logic Electrical Characteristics (Continued)
The following specifications apply for AGND e DGND e DGND(I O) e 0V VA e VD e a5 0VDC VD(I O) e a5 0 or
a3 0VDC REF IN e a1 225VDC fMCLK e 20 MHz Rs e 25X Boldface limits apply for TA e TJ e TMIN to TMAX all
other limits TA e TJ e 25 C (Notes 7 and 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
Operating
Standby
25 32 mA (max)
50 mA
ID
Digital Supply Current
Operating
MCLK e 0
6 8 mA (max)
65 mA
ID(I O)
Digital I O Supply Current
Operating VD(I O) e 5 0V
Operating VD(I O) e 3 0V
MCLK e 0 VD(I O) e 5 0V or 3 0V
31
16
17
6 mA (max)
4 mA (max)
mA
AC Electrical Characteristics MCLK Independent
The following specifications apply for AGND e DGND e DGND(I O) e 0V VA e VD e VD(I O) e a5 0VDC REF IN e
a1 225VDC fMCLK e 20 MHz tMCLK e 1 fMCLK tr e tf e 5 ns Rs e 25X CL (databus loading) e 50 pF pin Boldface
limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 7 and 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
fMCLK
Maximum MCLK Frequency
Minimum MCLK Frequency
20 MHz (min)
1 MHz (max)
MCLK Duty Cycle
30 40 % (min)
70 60 % (max)
tA
tCDSETUP
tCDHOLD
tD1H tD0H
tDACC
SYNC Setup of MCLK
Correction Data Valid to CLK Setup
Correction Data Valid to CLK Hold
RD High to DD0–DD7 TRI-STATE
Access Time Delay from RD Low to
DD0–DD7 Data Valid
5
14
b12
5
15
10 ns (min)
20 ns (min)
0 ns (min)
15 ns (max)
30 ns (max)
fSCLK
Maximum SCLK Frequency
SCLK Duty Cycle
20 MHz (min)
40 % (min)
60 % (max)
tSDI SDI Set-Up Time from SCLK
Rising Edge
3 10 ns (min)
tHDI SDI Hold Time from SCLK
Rising Edge
2 15 ns (min)
tDDO
Delay from SCLK Falling Edge to
SDO Data Valid
25 50 ns (max)
tHDO
SDO Hold Time from SCLK
Falling Edge
RL e 3k CL e 50 pF
30
50 ns (max)
5 ns (min)
tDELAY
DELAY from SCLK Falling Edge to
CS Rising or Falling Edge
5 10 ns (min)
tSETUP
Set-Up Time of CS Rising or Falling
Edge to SCLK Rising Edge
0 10 ns (min)
5 http www national com
5 Page 
Timing Diagrams (Continued)
Note Clamp signal only active during optical black pixels at beginning of line
DIAGRAM 7 CCD Timing
TL H 12814 – 15
Note Clamp signal only active during optical black pixels at beginning of line
DIAGRAM 8 CCD Timing (Even Odd CCDs)
TL H 12814 – 16
11 http www national com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LM9801.PDF ] | |
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