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M4A3-64 Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer M4A3-64
Beschreibung High Performance E2CMOS In-System Programmable Logic
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 30 Seiten
M4A3-64 Datasheet, Funktion
ispMACH4A CPLD Family
High Performance E2CMOS®
In-System Programmable Logic
FEATURES
High-performance, E2CMOS 3.3-V & 5-V CPLD families
Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and ret feature
— SpeedLockingTM performance for guaranteed xed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns tPD Commercial and 7.5ns tPD Industrial
— 182MHz fCNT
32 to 512 macrocells; 32 to 768 registers
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-FriendlyTM inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Advanced E2CMOS process provides high-performance, cost-effective solutions
Lead-free package options
Lead-
Free
Package
Options
Available!
Publication# ISPM4A Rev: M
Amendment/0
Issue Date: September 2006






M4A3-64 Datasheet, Funktion
Table 4. Architectural Summary of ispMACH 4A devices
Macrocell-I/O Cell Ratio
Input Switch Matrix
Input Registers
Central Switch Matrix
Output Switch Matrix
ispMACH 4A Devices
M4A3-64/32, M4A5-64/32
M4A3-96/48, M4A5-96/48
M4A3-128/64, M4A5-128/64
M4A3-192/96, M4A5-192/96
M4A3-256/128, M4A5-256/128
M4A3-384
M4A3-512
M4A3-32/32
M4A5-32/32
M4A3-64/64
M4A3-256/160
M4A3-256/192
2:1 1:1
Yes Yes1
Yes No
Yes Yes
Yes Yes
The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells
internally in a PAL block (Table 4).
The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through
the central switch matrix. This mechanism ensures that PAL blocks in ispMACH 4A devices communicate
with each other with consistent, predictable delays.
The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL devices on
a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single
programmable device; the software partitions the design into PAL blocks through the central switch matrix
so that the designer does not have to be concerned with the internal architecture of the device.
Each PAL block consists of:
Product-term array
Logic allocator
Macrocells
Output switch matrix
I/O cells
Input switch matrix
Clock generator
Notes:
1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.
6 ispMACH 4A Family

6 Page









M4A3-64 pdf, datenblatt
Configuration
D-type Register
T-type Register
D-type Latch
Table 8. Register/Latch Operation
Input(s)
CLK/LE 1
D=X 0,1, ()
D=0 ()
D=1 ()
T=X 0, 1, ()
T=0 ()
T=1 ()
D=X 1(0)
D=0 0(1)
D=1 0(1)
Q+
Q
0
1
Q
Q
Q
Q
0
1
Note:
1. Polarity of CLK/LE can be programmed
Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the
D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product terms are divided
between J and K (or S and R). When configured as J-K, S-R, or T-type, the extra product term must be used
on the XOR gate input for flip-flop emulation. In any register type, the polarity of the inputs can be
programmed.
The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode, with the
additional choice of either polarity of an individual product term clock in the asynchronous mode.
The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous reset and
preset are provided, each driven by a product term common to the entire PAL block.
Power-Up
Reset
PAL-Block
Initialization
Product Terms
AP AR
D/T/L Q
Power-Up
Preset
PAL-Block
Initialization
Product Terms
AP AR
D/L Q
a. Power-up reset
b. Power-up preset
17466G-012
Figure 7. Synchronous Mode Initialization Congurations
17466G-013
12 ispMACH 4A Family

12 Page





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