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APL5930 Schematic ( PDF Datasheet ) - ANPEC

Teilenummer APL5930
Beschreibung Ultra Low Dropout (0.23V Typical) Linear Regulator
Hersteller ANPEC
Logo ANPEC Logo 




Gesamt 17 Seiten
APL5930 Datasheet, Funktion
APL5930
3A, Ultra Low Dropout (0.23V Typical) Linear Regulator
Features
General Description
Compatible with APL5913
The APL5930 is a 3A ultra low dropout linear regulator.
Ultra Low Dropout
The IC needs two supply voltages, one is a control voltage
- 0.23V(typical) at 3A Output Current
Low ESR Output Capacitor (Multi-layer
Chip Capacitors (MLCC)) Applicable
0.8V Reference Voltage
High Output Accuracy
(V ) for the control circuitry, the other is a main supply
CNTL
voltage (VIN) for power conversion, to reduce power dissi-
pation and provide extremely low dropout voltage.
The APL5930 integrates many functions. A Power-On-
Reset (POR) circuit monitors both supply voltages on
VCNTL and VIN pins to prevent erroneous operations.
- ±1.5% over Line, Load, and Temperature Range The functions of thermal shutdown and current-limit pro-
Fast Transient Response
tect the device against thermal and current over-loads. A
Adjustable Output Voltage
POK indicates the output voltage status with a delay time
Power-On-Reset Monitoring on Both VCNTL and set internally. It can control other converter for power
VIN Pins
sequence. The APL5930 can be enabled by other power
Internal Soft-Start
systems. Pulling and holding the EN voltage below 0.4V
Current-Limit and Short Current-Limit Protections shuts off the output.
The APL5930 is available in a SOP-8P package which
Thermal Shutdown with Hysteresis
features small size as SOP-8 and an Exposed Pad to
Open-Drain VOUT Voltage Indicator (POK)
reduce the junction-to-case resistance to extend power
Low Shutdown Quiescent Current (<30 µA)
range of applications.
Shutdown/Enable Control Function
Simple SOP-8P Package with Exposed Pad
Applications
Lead Free and Green Devices Available
Front Side Bus VTT (1.2V/3A)
(RoHS Compliant)
Note Book PC Applications
Motherboard Applications
Pin Configuration
Simplified Application Circuit
GND 1
FB 2
VOUT 3
VOUT 4
8 EN
7 POK
6 VCNTL
5 VIN
SOP-8P (Top View)
= Exposed Pad
(connected to VIN plane for better heat dissipation)
POK
EN
Enable
VCNTL
POK VIN
VOUT
APL5930
EN FB
GND
VCNTL
VIN
VOUT
Optional
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
1
www.anpec.com.tw






APL5930 Datasheet, Funktion
APL5930
Typical Operating Characteristics (Cont.)
Dropout Voltage vs. Output Current
450
400 VCNTL = 5V
VOUT = 2.5V
350
300
250
TJ = 125 C
TJ = 75 C
TJ = 25 C
200
150
100
50
0
0
TJ = 0 C
TJ = - C
0.5 1 1.5 2 2.5
Output Current, IOUT (A)
3
0.808
Reference Voltage vs. Junction
Temperature
0.806
0.804
0.802
0.800
0.798
0.796
0.794
0.792
-50
-25 0 25 50 75 100 125
Junction Temperature (oC)
VIN Power Supply Rejection Ratio
(PSRR)
0
VCNTL=5V
VIN=1.8V
-10 VINPK-PK=100mV
VOUT=1.2V
-20
IOUT=3A
CIN=10µF
COUT=10µF
-30
-40
-50
-60
1000
10000
100000
Frequency (Hz)
1000000
VCNTL Power Supply Rejection Ratio
(PSRR)
0
VCNTL=4.6~5.4V
-10 VIN=1.8V
VOUT=1.2V
-20
IOUT=3A
CIN=COUT=10µF
-30
-40
-50
-60
-70
1000
10000
100000
Frequency (Hz)
1000000
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
6
www.anpec.com.tw

6 Page









APL5930 pdf, datenblatt
APL5930
Layout Consideration
1. Please solder the Exposed Pad on the VIN pad on
the top-layer of PCBs. The VIN pad must have wide
size to conduct heat into the ambient air through the
VIN plane and PCB as a heat sink.
2. Please place the input capacitors for VIN and VCNTL
pins near the pins as close as possible for
decoupling high-frequency ripples.
3. Ceramic decoupling capacitors for load must be
placed near the load as close as possible for
decoupling high-frequency ripples.
4. To place APL5930 and output capacitors near the
load reduces parasitic resistance and inductance
for excellent load transient response.
5. The negative pins of the input and output capacitors
and the GND pin must be connected to the ground
plane of the load.
6. Large current paths, shown by bold lines on the fig-
ure 1, must have wide tracks.
7. Place the R1, R2, and C1 near the APL5930 as close
as possible to avoid noise coupling.
8. Connect the ground of the R2 to the GND pin by us-
ing a dedicated track.
9. Connect the one pin of the R1 to the load for Kelvin
sensing.
10. Connect one pin of the C1 to the VOUT pin for reli-
able feedback compensation.
Thermal Consideration
Refer to the figure 2, the SOP-8P is a cost-effective pack-
age featuring a small size like a standard SOP-8 and a
bottom exposed pad to minimize the thermal resistance
of the package, being applicable to high current applica-
tions. The exposed pad must be soldered to the top-layer
VIN plane. The copper of the VIN plane on the Top layer
conducts heat into the PCB and ambient air. Please en-
large the area of the top-layer pad and the VIN plane to
reduce the case-to-ambient resistance (θCA).
102 mil
118 mil
18
27
SOP-8P
36
45
Ambient
Air
Top
VOUT
plane
Exposed
Die Pad
Top
VIN
plane
PCB
Figure 2
CCNTL
VCNTL
VCNTL
VIN
APL5930
VOUT
FB
GND
C1
R2
CIN
COUT
R1
VIN
VOUT
Load
Recommended Minimum Footprint
0.024
8765
0.138
Figure 1
12
0.050
34
Unit : Inch
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
12
www.anpec.com.tw

12 Page





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